Inline PCI-IOV adapter

Patent metadata

Field	Value
Publication number	US-9852087-B2
Application number	US-76400210-A
Country	US
Kind code	B2
Filing date	Apr 20, 2010
Priority date	Apr 20, 2010
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

First claim

The invention claimed is:

1. An apparatus comprising:
an inline PCI virtualizing device configured for connecting to a multi-root switch via a front-side bus and a physical back-side device via a back-side bus; and
a Soft Register Unit for facilitating register access, wherein register data is stored in an embedded RAM of the Soft Register Unit,
wherein the inline PCI virtualizing device and the physical back-side device are different devices,
wherein the multi-root switch is configured for connecting to each of a plurality of host CPUs via respective buses,
wherein the inline PCI virtualizing device is configured for retrofitting input/output (I/O) virtualization on the physical back-side device for sharing the physical back-side device by the plurality of host CPUs, and
wherein the inline PCI virtualizing device comprises one or more virtualized functions.

2. The apparatus of claim 1 , wherein the inline PCI virtualizing device is an ASIC.

3. The apparatus of claim 1 , wherein the inline PCI virtualizing device is integrated with the physical back-side device.

4. The apparatus of claim 1 , wherein the physical back-side device is a PCI device and the buses are PCI buses.

5. The apparatus of claim 1 , wherein the inline PCI virtualizing device facilitates address mapping to allow the physical back-side device to master DMA transactions that are mapped to the one or more virtualized functions.

6. The apparatus of claim 1 , wherein the inline PCI virtualizing device uses a notification queue to communicate register value changes to the physical back-side device.

7. The apparatus of claim 6 , wherein the notification queue is a sequence of memory locations that are written in with a sequence of messages, each containing an identification of a register and the value of the register.

8. The apparatus of claim 1 , wherein the plurality of host CPUs are on a single physical computing device.

9. The apparatus of claim 8 , wherein the single physical computing device is a blade system.

10. The apparatus of claim 1 , wherein the physical back-side device is a non-IOV device.

11. The apparatus of claim 10 , wherein the physical back-side non-IOV device is a Fibre Channel Host Bus Adapter.

12. The apparatus of claim 1 , wherein the inline PCI virtualizing device implements PCI configuration space for the physical back-side device.

13. The apparatus of claim 1 , wherein firmware on the physical back-side device indicates, in the high order bits of an address associated with a transaction, a physical function chosen to master the transaction.

14. An apparatus comprising:
an inline PCI virtualizing device configured for connecting to a host CPU via a front-side bus and a physical back-side device via a back-side bus; and
a Soft Register Unit for facilitating register access, wherein register data is stored in an embedded RAM of the Soft Register Unit,
wherein the inline PCI virtualizing device and the physical back-side device are different devices,
wherein the host CPU is configured for running a plurality of system images, each of the system images assigned a particular virtualized function (VF),
wherein the inline PCI virtualizing device is configured for retrofitting input/output (I/O) virtualization on the physical back-side device for sharing the physical back-side device by the plurality of system images, and
wherein the inline PCI virtualizing device comprises one or more virtualized functions.

15. The apparatus of claim 14 , wherein the inline PCI virtualizing device is an ASIC.

16. The apparatus of claim 14 , wherein the inline PCI virtualizing device is integrated with the physical back-side device.

17. The apparatus of claim 14 , wherein the physical back-side device is a PCI device and the buses are PCI buses.

18. The apparatus of claim 14 , wherein the inline PCI virtualizing device facilitates address mapping to allow the physical back-side device to master DMA transactions that are mapped to the one or more virtualized functions.

19. The apparatus of claim 14 , wherein the inline PCI virtualizing device uses a notification queue to communicate register value changes to the physical back-side device.

20. The apparatus of claim 19 , wherein the notification queue is a sequence of memory locations that are written in with a sequence of messages, each containing an identification of a register and the value of the register.

21. The apparatus of claim 14 , wherein the physical back-side device is a non-IOV device.

22. The apparatus of claim 21 , wherein the physical back-side non-IOV device is a Fibre Channel Host Bus Adapter.

23. The apparatus of claim 14 , wherein the inline PCI virtualizing device implements PCI configuration space for the physical back-side device.

24. The apparatus of claim 14 , wherein firmware on the physical back-side device indicates, in the high order bits of an address associated with a transaction, a physical function chosen to master the transaction.

25. The apparatus of claim 1 , wherein the inline PCI virtualizing device includes a plurality of sets of registers, each of the sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the physical back-side device.

26. The apparatus of claim 14 , wherein the inline PCI virtualizing device includes a plurality of sets of registers, each of the sets of registers accessible by a corresponding system image of the plurality of system images and implementing functionalities of the physical back-side device.

27. A method comprising:
connecting an inline PCI virtualizing device to a multi-root switch, wherein the multi-root switch is configured for connecting to each of a plurality of host CPUs via respective buses;
connecting the inline PCI virtualizing device to a physical device, wherein the inline PCI virtualizing device and the physical device are different devices;
retrofitting, via the inline PCI virtualizing device, input/output (I/O) virtualization on the physical device for sharing the physical device by the plurality of host CPUs;
generating one or more virtualized functions within the inline PCI virtualizing device; and
storing register data in an embedded RAM of a Soft Register Unit for facilitating register access.

28. The method of claim 27 , further comprising:
facilitating, via the inline PCI virtualizing device, address mapping to allow the physical device to master DMA transactions that are mapped to the one or more virtualized functions.

29. The method of claim 27 , further comprising:
using, via the inline PCI virtualizing device, a notification queue to communicate register value changes to the physical device.

30. The method of claim 27 , further comprising:
implementing, via the inline PCI virtualizing device, PCI configuration space for the physical device.

31. A method comprising:
connecting an inline PCI virtualizing device to a host CPU;
generating one or more virtualized functions within the inline PCI virtualizing device, wherein the host CPU is configured for running a plurality of system images, each of the system images assigned a particular virtualized function (VF) of the one or more virtualized functions;
connecting the inline PCI virtualizing device to a physical device, wherein the inline PCI virtuali

Assignees

• Williams James B
• Clayton Shawn Adam
• Gutierrez Maria Clara
• Nicolson Iv Alexander
• Smart James Winston
• Wood John Leland
• Duckman David James
• Lindeborg Carl John
• Leavitt William Irving
• Avago Technologies General Ip

Inventors

• Williams James B
• Clayton Shawn Adam
• Gutierrez Maria Clara
• Nicolson Iv Alexander
• Smart James Winston
• Wood John Leland
• Duckman David James
• Lindeborg Carl John
• Leavitt William Irving

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic