Data mapping for non-volatile storage

Patent metadata

Field	Value
Publication number	US-9852078-B2
Application number	US-201514928454-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	May 8, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, a mapping between caches and sense amplifiers in a sensing circuit is modified by using dual data buses. One bus is used for same-tier transfers and the other is used for cross-tier transfers. Each tier comprises a set of sense amplifiers and a corresponding set of caches. This approach does not require a modification of the input/output path which is connected to the sensing circuitry.

First claim

What is claimed is:

1. A circuit, comprising:
a plurality of sense amplifiers and a plurality of caches, one cache per sense amplifier, wherein each sense amplifier is connected to a respective memory cell in a word line via a respective bit line, the respective bit lines comprise a first set of every other bit line and a second set of every other bit line, and the plurality of sense amplifiers and the plurality of caches are arranged in a plurality of pairs of tiers, each pair of tiers comprising:
a first tier and a second tier;
the first tier comprising an integer number N>1 of sense amplifiers including N/2 sense amplifiers associated with the first set of every other bit line and N/2 sense amplifiers associated with the second set of every other bit line;
the first tier also comprising N caches including a first set of N/2 caches and a second set of N/2 caches;
the second tier comprising N sense amplifiers including N/2 sense amplifiers associated with the first set of every other bit line and N/2 sense amplifiers associated with the second set of every other bit line; and
the second tier also comprising N caches including a first set of N/2 caches and a second set of N/2 caches;

wherein each pair of tiers comprises switchable paths which are configurable in a first mode in which the N/2 sense amplifiers of the second tier associated with the first set of every other bit line are connected to the first set of N/2 caches of the first tier and the N/2 sense amplifiers of the first tier associated with the first set of every other bit line are connected to the second set of N/2 caches of the first tier, and in a second mode in which the N/2 sense amplifiers of the second tier associated with the second set of every other bit line are connected to the second set of N/2 caches of the second tier and the N/2 sense amplifiers of the first tier associated with the second set of every other bit line are connected to the first set of N/2 caches of the second tier.

2. The circuit of claim 1 , wherein:
the first set of every other bit line comprises even-numbered bit lines and the second set of every other bit line comprises odd-numbered bit lines, or the first set of every other bit line comprises odd-numbered bit lines and the second set of every other bit line comprises even-numbered bit lines.

3. The circuit of claim 1 , wherein:
in the first tier, the first set of N/2 caches comprises a set of adjacent caches and the second set of N/2 caches comprises a set of adjacent caches; and
in the second tier, the first set of N/2 caches comprises a set of adjacent caches and the second set of N/2 caches comprises a set of adjacent caches.

4. The circuit of claim 1 , wherein the switchable paths are configurable in a third mode in which:
a first set of N/2 sense amplifiers of the first tier associated with N/2 respective adjacent bit lines are connected to the second set of N/2 caches of the first tier;
a second set of N/2 sense amplifiers of the first tier associated with N/2 respective adjacent bit lines are connected to the first set of N/2 caches of the first tier;
a first set of N/2 sense amplifiers of the second tier associated with N/2 respective adjacent bit lines are connected to the first set of N/2 caches of the second tier; and
a second set of N/2 sense amplifiers of the second tier associated with N/2 respective adjacent bit lines are connected to the second set of N/2 caches of the second tier.

5. The circuit of claim 1 , further comprising:
N input/output paths; and
N cache access lines, each cache access line connected to a respective input/output path of the N input/output paths, to a respective cache of the first tier and to a respective cache of the second tier.

6. The circuit of claim 1 , wherein for each pair of tiers, the switchable paths comprise:
a first data bus of the first tier connected to the N sense amplifiers of the first tier and the first set of N/2 caches of the first tier;
a second data bus of the first tier connected to the N sense amplifiers of the first tier and the second set of N/2 caches of the first tier;
a first data bus of the second tier connected to N sense amplifiers of the second tier and the first set of N/2 caches of the second tier;
a second data bus of the second tier connected to the N sense amplifiers of the second tier and the second set of N/2 caches of the second tier;
a first jumper connected to the first data bus of the first tier and the second data bus of the second tier; and
a second jumper connected to the second data bus of the first tier and the first data bus of the second tier.

7. The circuit of claim 6 , further comprising:
a first control line connected to a control gate of a transistor in the second data bus of the first tier and to a control gate of a transistor in the first jumper;
a second control line connected to a control gate of a transistor in the first data bus of the first tier and to a control gate of a transistor in the first data bus of the second tier;
a third control line connected to a control gate of a transistor in the second jumper and to a control gate of a transistor in the second data bus of the second tier; and
a fourth control line connected to a control gate of a transistor in the second jumper, and to a control gate of a transistor in the first jumper.

8. The circuit of claim 7 , further comprising a control circuit associated with the first, second, third and fourth control lines, wherein the control circuit is configured to:
in the first mode, provide an ON voltage on the first and fourth control lines and provide an OFF voltage on the second and third control lines; and
in the second mode, provide an ON voltage on the third and fourth control lines and provide an OFF voltage on the first and second control lines.

9. The circuit of claim 6 , further comprising:
switches associated with the first and second data bus of the first tier, the first and second data bus of the second tier, and the first and second jumpers, wherein for each pair of tiers, the switches are configurable in a first mode in which:
the first data bus of the first tier, the first jumper and the second data bus of the second tier connect the N/2 sense amplifiers of the second tier associated with the first set of every other bit line with the first set of N/2 caches of the first tier; and
the second data bus of the first tier connects the N/2 sense amplifiers of the first tier associated with the first set of every other bit line with the second set of N/2 caches of the first tier.

10. The circuit of claim 9 , wherein for each pair of tiers, the switches are configurable in a second mode at a different time than the first mode in which:
the first data bus of the first tier, the second jumper and the first data bus of the second tier connect the N/2 sense amplifiers of the first tier associated with the second set of every other bit line with the first set of N/2 caches of the second tier; and
the second data bus of the second tier connects the N/2 sense amplifiers of the second tier associated with the second set of every other bit line with the second set of N/2 caches of the second tier.

11. The circuit of claim 9 , further comprising a control circuit, the control circuit in a programming operation is configured to in the first mode:
transfer a first half of a first word of data from the first set of N/2 caches of the first tier to the N/2 sense amplifiers of the second tier associated with the first set of every other bit line via the first data bus of the first tier, the first jumper and the second data bus of the second tier; and
transfer a second half of the first word of data from the seco

Assignees

• Sandisk Technologies Llc

Inventors

• Zaitsu Shingo
• Kato Yosuke
• Ookuma Naoki

Classifications

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title