Memory device, memory system and method of operating memory device

Patent metadata

Field	Value
Publication number	US-9851912-B2
Application number	US-201715443647-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Jul 2, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device including a memory cell array, the memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of memory cell strings, each of the memory cell strings including a pillar extending in a direction vertical to a substrate and a plurality of transistors stacked along the pillar,
the memory device comprising:
a first block region including at least one memory block and having a first distance from a center of the memory cell array;
a second block region including at least one memory block and having a second distance from the center of the memory cell array; and
a control logic configured to store a first algorithm and a second algorithm, the first algorithm and the second algorithm being associated with the first block region and the second block region respectively, and further configured to control a first operation on the first block region using the first algorithm and a second operation on the second block region using the second algorithm respectively,

wherein the first algorithm and the second algorithm are different when the first distance and the second distance are different.

2. The memory device of claim 1 , wherein the control logic further configured to store a block region information which represents a relationship between the block regions and the memory blocks, and one single algorithm is applied on all of the memory blocks in a block region.

3. The memory device of claim 2 , wherein the block region information is modified according to an operation cycle count or a data retention period.

4. The memory device of claim 1 , wherein the first operation and the second operation comprises basic operations and auxiliary operations respectively, the basic operations including at least one of program operation, erase operation, and read operation, and the auxiliary operations including at least one of a pre-program operation, a post-program operation, a sub-block dividing operation, a count pulse program operation, a soft program operation, an off-string search operation, a read recovery operation using retention pre-defined table (PDT), and a read recovery operation using endurance pre-defined table (PDT).

5. The memory device of claim 4 , wherein the pre-program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

6. The memory device of claim 4 , wherein the post-program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

7. The memory device of claim 4 , wherein the sub-block dividing operation is included in the first algorithm and is not included in the second algorithm when the first distance is shorter than the second distance.

8. The memory device of claim 4 , wherein the count pulse program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

9. The memory device of claim 4 , wherein the soft program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

10. The memory device of claim 4 , wherein the off-string search operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

11. The memory device of claim 4 , wherein the read recovery operation using retention pre-defined table (PDT) is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

12. The memory device of claim 4 , wherein the read recovery operation using endurance pre-defined table (PDT) is included in the first algorithm and is not included in the second algorithm when the first distance is shorter than the second distance.

13. The memory device of claim 4 , wherein the control logic further configured to store a third algorithm and a fourth algorithm, and if an operation cycle count is equal to or less than a threshold value, the auxiliary operation is performed on the first and the second block regions using the first algorithm and the second algorithm respectively, and if the operation cycle count is greater than the threshold value, the auxiliary operation is performed on the first and the second block regions using a third algorithm and the fourth algorithm respectively,
wherein the third algorithm and the fourth algorithm are determined to prevent a difference in operation speed of each block region caused from the increase of the operation cycle count.

14. The memory device of claim 1 , wherein at least one of the first algorithm and the second algorithm is modified according to at least one of an operation cycle count or a data retention period.

15. A three-dimensional (3D) memory device including a memory cell array, the memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of memory cell strings, each of the memory cell strings including a pillar extending in a direction vertical to a substrate and a plurality of transistors stacked along the pillar,
the memory device comprising:
a first memory block having a first distance from a center of the memory cell array;
a second memory block having a second distance from the center of the memory cell array; and
a control logic configured to store a first algorithm and a second algorithm, the first algorithm and the second algorithm being associated with the first memory block and the second memory block respectively, and further configured to control a first operation on the first memory block using the first algorithm and a second operation on the second memory block using the second algorithm respectively,

wherein the first algorithm and the second algorithm are different when the first distance and the second distance are different.

16. The memory device of claim 15 , wherein the first operation and the second operation comprises basic operations and auxiliary operations respectively, the basic operations including at least one of a program operation, an erase operation, and a read operation, and the auxiliary operations including at least one of a pre-program operation, a post-program operation, a sub-block dividing operation, a count pulse program operation, a soft program operation, an off-string search operation, a read recovery operation using retention pre-defined table (PDT), and a read recovery operation using endurance pre-defined table (PDT).

17. The memory device of claim 16 , wherein the pre-program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

18. The memory device of claim 16 , wherein the post-program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shorter than the second distance.

19. The memory device of claim 16 , wherein the sub-block dividing operation is included in the first algorithm and is not included in the second algorithm when the first distance is shorter than the second distance.

20. The memory device of claim 16 , wherein the count pulse program operation is not included in the first algorithm and is included in the second algorithm when the first distance is shor

Assignees

• Nam Sang-Wan
• Kim Doo-Hyun
• Byeon Dae-Seok
• Yoon Chi-Weon
• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Kim Doo-Hyun
• Byeon Dae-Seok
• Yoon Chi-Weon

Classifications

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title