Test probe substrate

Patent metadata

Field	Value
Publication number	US-9851379-B2
Application number	US-201715469497-A
Country	US
Kind code	B2
Filing date	Mar 25, 2017
Priority date	Sep 24, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

First claim

What is claimed is:

1. A method comprising:
obtaining a structure comprising a test probe substrate including a top surface, a plurality of first and second contact locations arranged in rows and columns, one or more of the second contact locations being misaligned with respect to the first contact locations, and electrical conductors within the substrate, the first and second contact locations being electrically connected to one or more of the electrical conductors;
forming a first dielectric layer over the top surface of the substrate;
forming a plurality of first openings within the first dielectric layer, each of the first openings corresponding to one of the first and second contact locations;
forming one or more lateral extensions of the first openings that correspond to the one or more misaligned second contact locations within the first dielectric layer, each of the one or more lateral extensions extending radially with respect to one of the first openings;
depositing an electrically conductive material within the first openings and lateral extensions such that the electrically conductive material contacts the first and second contact locations;
depositing a second dielectric layer over the first dielectric layer;
forming a plurality of second openings within the second dielectric layer, the plurality of second openings being arranged in parallel rows without misalignment, one or more of the second openings being aligned with and communicating with the one or more lateral extensions, others of the second openings being aligned with the first openings that correspond to the first contact locations;
depositing an additional electrically conductive material within the second openings to form an array of electrical contact regions electrically connected to the first and second contact locations, and
planarizing the second dielectric layer.

2. The method of claim 1 , wherein the step of depositing the electrically conductive material within the first openings and the one or more lateral extensions includes injecting molten solder.

3. The method of claim 2 , wherein the substrate is comprised of a ceramic material, glass, silicon or an organic material and the first dielectric layer comprises a dielectric adhesive.

4. The method of claim 2 , further including the steps of attaching an interposer layer having a bottom surface and a top surface to the substrate over the second dielectric layer, the interposer layer including electrically conductive probe tips extending from the top surface of the interposer layer, and causing the electrical connection of the probe tips to the contact locations of the substrate.

5. The method of claim 4 , wherein the step of causing the electrical connection of the probe tips to the contact locations of the substrate includes causing solder reflow between the electrical contact regions and the bottom surface of the interposer layer.

6. The method of claim 5 , wherein the second dielectric layer is deposited directly on the first dielectric layer and the first dielectric layer is deposited on the top surface of the substrate.

7. The method of claim 1 , further including the step of planarizing the first dielectric layer.

8. The method of claim 1 , further including the steps of mapping three dimensional coordinates of the contact locations, storing the mapped coordinates electronically in a memory device, comparing the stored coordinates to a set of predetermined coordinate positions, determining a set of stored coordinates that do not match the set of predetermined coordinate positions, wherein at least the step of forming the one or more lateral extensions is performed using the set of stored coordinates that do not match the set of predetermined coordinate positions.

9. The method of claim 1 , wherein the one or more second contact locations includes a plurality of second contact locations misaligned with respect to the first contact locations, the one or more lateral extensions including a plurality of lateral extensions.

10. The method of claim 9 , further including planarizing the first dielectric layer following depositing the electrically conductive material.

11. The method of claim 9 , wherein the first openings include round portions and the lateral extensions comprise tails extending radially from the round portions, each of the tails extending in one of a plurality of selected directions with respect to the round portions of the plurality of first openings.

12. The method of claim 11 , wherein the rows of first and second contact locations are not entirely parallel to each other.

13. The method of claim 12 , wherein the substrate is a low temperature co-fire ceramic substrate.

14. The method of claim 12 , further including depositing finish metallurgy on the electrical contact regions, the finish metallurgy being positioned above each of the second openings.

15. The method of claim 14 , wherein the finish metallurgy comprises solder interconnection bumps.

16. The method of claim 1 , further including determining whether the second contact locations are misaligned by comparing the first and second contact locations with a set of coordinate positions of an electrical contact surface of test hardware.

17. The method of claim 16 , wherein forming the one or more lateral extensions of the first openings further includes extending the lateral extensions in one or more directions based on the coordinate positions of the electrical contact surface of the test hardware.

Assignees

• IBM

Inventors

• Dang Bing
• Knickerbocker John U
• Nah Jae-Woong
• Trzcinski Robert E
• Tsang Cornelia Kang-I

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title