Integrated circuit package and method of forming same

Patent metadata

Field	Value
Publication number	US-9850126-B2
Application number	US-201514986189-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.

First claim

What is claimed is:

1. A method comprising:
attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures;
forming a release layer over the first die and the second die;
injecting an encapsulant between the carrier and the release layer, wherein the encapsulant is over the carrier and under the release layer, and in a gap between the first and second die; and
forming one or more redistribution layers (RDLs) over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.

2. The method of claim 1 , further comprising attaching a third die to the one or more RDLs, the one or more RDLs being interposed between the encapsulant and the third die.

3. The method of claim 1 , wherein a topmost surface of the encapsulant is below a topmost surface of the first die.

4. The method of claim 1 , wherein a topmost surface of the encapsulant is below a topmost surface of the second contact pad.

5. The method of claim 1 , wherein the first contact pad is embedded in a first dielectric layer.

6. The method of claim 5 , wherein the second contact pad extends over a second dielectric layer, the second contact pad being in electrical contact with a through via in the second die.

7. The method of claim 1 , wherein the first die is a CMOS die, and wherein the second die is a MEMS die.

8. A method comprising:
attaching a first side of a first die to a carrier, the first die having:
a first contact pad on a second side of the first die, the second side of the first die being opposite the first side of the first die; and
a first insulating layer on the second side of the first die, at least a portion of the first contact pad being exposed through an opening in the first insulating layer;

attaching a first side of a second die to the carrier, the second die having:
a through via, the through via extending from the first side of the second die to a second side of the second die, the second side of the second die being opposite the first side of the second die;
a second insulating layer on the second side of the second die, at least a portion of the through via extending through the second insulating layer; and
a second contact pad over the second insulating layer, the second contact pad contacting the through via;

laminating a release layer over top surfaces of the first contact pad, the second contact pad, the first insulating layer and the second insulating layer;
injecting a first encapsulant between the carrier and the release layer, and in a gap between the first die and the second die; and
forming one or more redistribution layers (RDLs) over the first die, the second die and the first encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.

9. The method of claim 8 , further comprising:
attaching one or more dies to the one or more RDLs, the one or more RDLs being interposed between the one or more dies and the first encapsulant; and
attaching the one or more RDLs to a circuit board, the circuit board having an opening, the one or more dies extending through the opening.

10. The method of claim 8 , further comprising attaching a third die to the one or more RDLs, the one or more RDLs being interposed between the first die and the third die.

11. The method of claim 10 , further comprising forming a second encapsulant over the one or more RDLs, at least a portion of the second encapsulant extending along a sidewall of the third die.

12. The method of claim 8 , wherein injecting the first encapsulant comprises forcing the first encapsulant into in the gap between the first die and the second die using a plunger.

13. The method of claim 8 , wherein a topmost surface of the first contact pad is not coplanar with a topmost surface of the first encapsulant.

14. The method of claim 13 , wherein a topmost surface of the second contact pad is not coplanar with the topmost surface of the first encapsulant.

15. A method comprising:
forming a release layer over a first die, a second die, a third die, and a fourth die, the first, second, third, and fourth dies over and connected to a carrier;
injecting an encapsulant in gaps between the first die, the second die, the third die, and the fourth die, wherein a topmost surface of the encapsulant is below a topmost surface of the first die, a topmost surface of the second die, a topmost surface of the third die, and a topmost surface of the fourth die;
forming one or more redistribution layers (RDLs) over the first die, the second die, the third die, the fourth die, and the encapsulant;
forming connectors over the one or more RDLs;
de-bonding the carrier to leave a resulting structure comprising the first die, the second die, the third die, the fourth die, the encapsulant, the one or more RDLs, and the connectors over the one or more RDLs; and
dicing the resulting structure to form a first integrated circuit package and a second integrated circuit package, the first integrated circuit package comprising the first die, the second die, a first subset of the encapsulant, a first subset of the one or more RDLs, and a first subset of the connectors over the first subset of the one or more RDLs, the second integrated circuit package comprising the third die, the fourth die, a second subset of the encapsulant, a second subset of the one or more RDLs, and a second subset of the connectors over the second subset of the one or more RDLs.

16. The method of claim 15 further comprising attaching one or more fifth dies over the first subset of the connectors of the first integrated circuit package.

17. The method of claim 15 further comprising attaching one or more sixth dies over the second subset of the connectors of the second integrated circuit package.

18. The method of claim 15 wherein the first die and the third die are CMOS dies.

19. The method of claim 18 wherein the second die and the fourth die are ambient sensors.

20. The method of claim 18 further comprising testing the first integrated circuit package and the second integrated circuit package to identify known good packages (KGPs).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Kuo Lung
• Liu Chung-Shi
• Tsai Hao-Yi
• Chen Yu-Feng
• Cheng Yu-Jen

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title