Multi-rate clock buffer

Patent metadata

Field	Value
Publication number	US-9847776-B2
Application number	US-201414330987-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

First claim

What is claimed is:

1. A circuit comprising:
a driver circuit configured to receive a clock signal and to output a modified clock signal based on the received clock signal, the modified clock signal being configured to drive a load circuit;
a first tuned circuit electrically coupled to the driver circuit and including one or more components configured with respect to the driver circuit and the load circuit such that the first tuned circuit and the driver circuit are collectively tuned according to a first frequency range, the first tuned circuit configured to be active when a rate of the clock signal is within the first frequency range and configured to be inactive when the rate of the clock signal is outside of the first frequency range, wherein the first tuned circuit includes:
a first tuning element electrically coupled to an output terminal of the driver circuit, wherein the output terminal is configured to output the modified clock signal, wherein the first tuning element includes one or more of: a resistor and an inductor; and
a first transistor electrically coupled between the first tuning element and a supply voltage without another tuning element being coupled between the first transistor and the supply voltage, the first transistor being configured to receive a first control signal configured to turn the first transistor on when the rate of the clock signal is within the first frequency range and to turn the first transistor off when the rate of the clock signal is outside of the first frequency range, wherein the first tuned circuit is active when the first transistor is on and is inactive when the first transistor is off; and

a second tuned circuit electrically coupled to the driver circuit and including one or more components configured with respect to the driver circuit and the load circuit such that the second tuned circuit and the driver circuit are collectively tuned according to a second frequency range that is different from the first frequency range, the second tuned circuit configured to be active when the rate of the clock signal is within the second frequency range and configured to be inactive when the rate of the clock signal is outside of the second frequency range, wherein the second tuned circuit includes:
a second tuning element electrically coupled to the output terminal; and
a second transistor electrically coupled between the second tuning element and the supply voltage, the second transistor being configured to receive a second control signal configured to turn the second transistor on when the rate of the clock signal is within the second frequency range and to turn the second transistor off when the rate of the clock signal is outside of the second frequency range, wherein the second tuned circuit is active when the second transistor is on and is inactive when the second transistor is off.

2. The circuit of claim 1 , wherein:
the clock signal is a differential clock signal that includes a first clock signal and a second clock signal;
the modified clock signal is a differential signal that includes a first modified clock signal and a second modified clock signal;
the output terminal of the driver circuit includes a first output terminal configured to output the first modified clock signal and a second output terminal configured to output the second modified clock signal; and
the driver circuit further includes:
a first input terminal configured to receive the first clock signal;
a second input terminal configured to receive the second clock signal;
a current-source node;
a current source electrically coupled between the current-source node and ground;
a first driver-transistor including:
a first-driver base electrically coupled to the first input terminal;
a first-driver collector electrically coupled to the second output terminal; and
a first-driver emitter electrically coupled to the current-source node; and

a second driver-transistor including:
a second-driver base electrically coupled to the second input terminal;
a second-driver collector electrically coupled to the first output terminal; and
a second-driver emitter electrically coupled to the current-source node.

3. The circuit of claim 2 , wherein:
the first tuned circuit includes one or more first tuning elements configured with respect to the current source and the load circuit such that the first tuned circuit and the driver circuit are collectively tuned according to the first frequency range; and
the second tuned circuit includes one or more second tuning elements configured with respect to the current source and the load circuit such that the second tuned circuit and the driver circuit are collectively tuned according to the second frequency range.

4. The circuit of claim 3 , wherein the one or more first tuning elements and the one or more second tuning elements include one or more of a resistor and an inductor.

5. The circuit of claim 2 , wherein:
the first tuning element is a first first-tuned tuning element;
the first transistor is a first first-tuned transistor;
the second tuning element is a first second-tuned tuning element;
the second transistor is a first second-tuned transistor;
the first tuned circuit further includes:
a second first-tuned tuning element electrically coupled to the first output terminal; and
a second first-tuned transistor electrically coupled between the second first-tuned tuning element and the supply voltage, the second first-tuned transistor being configured to receive the first control signal which is configured to turn the second first-tuned transistor on when the rate of the clock signal is within the first frequency range and to turn the second first-tuned transistor off when the rate of the clock signal is outside of the first frequency range; and

the second tuned circuit further includes:
a second second-tuned tuning element electrically coupled to the first output terminal; and
a second second-tuned transistor electrically coupled between the second second-tuned tuning element and the supply voltage, the second second-tuned transistor being configured to receive the second control signal which is configured to turn the second second-tuned transistor on when the rate of the clock signal is within the second frequency range and to turn the second second-tuned transistor off when the rate of the clock signal is outside of the second frequency range.

6. The circuit of claim 2 , wherein:
the first tuning element is electrically coupled to the second output terminal; and
the second tuning element is electrically coupled to the first output terminal.

7. The circuit of claim 2 , wherein:
the first tuning element is electrically coupled to the first output terminal; and
the second tuning element is electrically coupled to the second output terminal.

8. The circuit of claim 1 , further comprising a control unit configured to:
set the first control signal such that the first tuned circuit is active when the rate of the clock signal is within the first frequency range;
set the second control signal such that the second tuned circuit is inactive when the rate of the clock signal is within the first frequency range;
set the first control signal such that the first tuned circuit is inactive when the rate of the clock signal is within the second frequency range; and
set the second control signal such that the second tuned circuit is active when the rate of the clock signal is within the second frequency range.

9. The circuit of claim 1 , wherein the first frequency range includes approximately 25 to 30 gigahertz (GHz), 19 to 23 GHz, or 9 to 15 GHz.

10. The circuit of claim 1 , wherein the second frequency range includes approximatel

Assignees

• Finisar Corp

Inventors

• Kalogerakis Georgios
• Nguyen The'Linh
• Moran Timothy G

Classifications

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title

• H04L7/04

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H03K5/02

  by amplifying (H03K5/04 takes precedence) · CPC title