Flip-flop circuit
US-2015381154-A1 · Dec 31, 2015 · US
Buffer, and multiphase clock generator, semiconductor apparatus and system using the same
US9847775B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9847775-B2 |
| Application number | US-201615279727-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2016 |
| Priority date | May 12, 2016 |
| Publication date | Dec 19, 2017 |
| Grant date | Dec 19, 2017 |
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- Title
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Abstract
Official abstract text for this publication.
A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A buffer comprising: an amplification circuit configured to change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals; an amplification current generation circuit configured to provide currents having different magnitudes to the first and second output nodes during a first operation period, the amplification current generation circuit providing currents having the same magnitude to the first a…
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Classifications
- H03K3/35625Primary
Electricity · mapped topic
Electricity · mapped topic
- H03M9/00Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9847775B2 cover?
- A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a fi…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K3/35625. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).