Switched capacitor gain stage

Patent metadata

Field	Value
Publication number	US-9847760-B1
Application number	US-201715620171-A
Country	US
Kind code	B1
Filing date	Jun 12, 2017
Priority date	Jun 13, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

First claim

What is claimed is:

1. A circuit comprising:
a gain stage block coupled to an input voltage through a first switch;
a first capacitor coupled between the first switch and a ground terminal;
a second capacitor coupled between the first switch and a second switch; and
a third switch coupled between the second capacitor and a fixed terminal of the gain stage block.

2. The circuit of claim 1 , wherein the fixed terminal is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block, and a voltage generated at the fixed terminal and the input voltage have a non-inverting relationship.

3. The circuit of claim 1 , wherein one end of the second switch is coupled to the ground terminal.

4. The circuit of claim 1 , wherein the gain stage block includes a transistor whose gate terminal receives the input voltage through the first switch.

5. The circuit of claim 4 , wherein the fixed terminal of the gain stage block is coupled to a source terminal of the transistor and the third switch.

6. The circuit of claim 4 , wherein a drain terminal of the transistor is coupled to a source voltage.

7. The circuit of claim 1 , wherein in a sampling mode:
the first switch and the second switch are closed;
the third switch is opened; and
the first capacitor and the second capacitor are charged to the input voltage.

8. The circuit of claim 1 , wherein in a hold mode:
the first switch and the second switch are opened;
the third switch is closed; and
the first capacitor is charged to a third voltage.

9. The circuit of claim 8 , wherein the voltage generated at the fixed terminal is equal to a product of the third voltage and a gain of the gain stage block.

10. A method comprising:
closing a first switch and a second switch;
opening a third switch;
charging a first capacitor and a second capacitor to an input voltage, the first capacitor and the second capacitor are coupled to a gain stage block;
opening the first switch and the second switch;
closing the third switch; and
charging the first capacitor to a third voltage, wherein a voltage generated at a fixed terminal of the gain stage block is proportional to the third voltage.

11. The method of claim 10 further comprising:
providing the input voltage to the gain stage block through the first switch; and
providing a source voltage to the gain stage block.

12. The method of claim 10 , wherein the fixed terminal is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block, and the voltage generated at the fixed terminal and the input voltage have a non-inverting relationship.

13. The method of claim 10 further comprising:
coupling the first capacitor between the first switch and a ground terminal;
coupling the second capacitor between the first switch and the second switch; and
coupling the third switch between the second capacitor and the fixed terminal of the gain stage block.

14. The method of claim 10 , wherein the second switch is coupled between the second capacitor and the ground terminal.

15. A transceiver comprising:
a gain stage configured to receive an input voltage; and
an analog to digital converter (ADC) coupled to the gain stage, and configured to generate a digital output signal, wherein at least one of the gain stage and the ADC comprises a switched capacitor gain stage circuit, the switched capacitor gain stage circuit comprising:
a gain stage block coupled to the input voltage through a first switch;
a first capacitor coupled between the first switch and a ground terminal;
a second capacitor coupled between the first switch and a second switch; and
a third switch coupled between the second capacitor and a fixed terminal of the gain stage block.

16. The transceiver of claim 15 , wherein the fixed terminal is coupled to at least one of an output terminal and an intermediate terminal of the gain stage block, and a voltage generated at the fixed terminal and the input voltage have a non-inverting relationship.

17. The transceiver of claim 15 , wherein the gain stage block is a transistor whose gate terminal receives the input voltage through the first switch and whose drain terminal is coupled to a source voltage.

18. The transceiver of claim 17 , wherein the fixed terminal of the gain stage block is coupled to a source terminal of the transistor and the third switch.

19. The transceiver of claim 15 , wherein in a sampling mode:
the first switch and the second switch are closed;
the third switch is opened; and
the first capacitor and the second capacitor are charged to the input voltage.

20. The transceiver of claim 15 , wherein in a hold mode:
the first switch and the second switch are opened;
the third switch is closed; and
the first capacitor is charged to a third voltage.

Assignees

• Texas Instruments Inc

Inventors

• Dusad Shagun
• Joish Rajendrakumar

Classifications

• H03F3/005 Primary

  using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H04B1/40 Primary

  Circuits · CPC title

• G11C27/026

  associated with an amplifier (G11C27/028 takes precedence) · CPC title

• H03F3/193 Primary

  with field-effect devices (H03F3/195 takes precedence) · CPC title