Charge sharing analog computation circuitry and applications

Patent metadata

Field	Value
Publication number	US-9312831-B2
Application number	US-201314043009-A
Country	US
Kind code	B2
Filing date	Oct 1, 2013
Priority date	Aug 18, 2010
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

First claim

What is claimed is:

1. A method for mapping input values to capacitor values to implement a programmable discrete time analog filter, comprising:
accepting a plurality of filter coefficient input values;
determining a plurality of digital configuration values for a plurality of configurable capacitors in a programmable discrete time analog filter, wherein the plurality of digital configuration values are determined according to a non-linear mapping of the filter coefficient input values to the digital configuration values; and
providing the digital configuration values for configuration of the programmable filter.

2. The method of claim 1 , further comprising providing a passive signal scaling circuit.

3. The method of claim 1 , wherein the filter coefficient input values are floating point numbers and the non-linear mapping comprises mapping the floating point numbers to DAC values.

4. The method of claim 1 , wherein each of the digital configuration values is for configuring capacitance of a capacitive element of the plurality of configurable capacitors.

5. The method of claim 1 , wherein the programmable discrete time analog filter processes analog biological signals.

6. The method of claim 1 , wherein the programmable discrete time analog filter processes one of analog hearing aid signals and analog ultrasound signals.

7. The method of claim 1 , further comprising providing at least one charge sharing stage wherein at least a subset of the plurality of configurable capacitors share charges.

8. The method of claim 1 , wherein the programmable filter is configured as one of a finite impulse response filter and an infinite impulse response filter.

9. The method of claim 1 , wherein the programmable filter is one of a low-pass filter, a high-pass filter, a band-pass filter, a notch filter, and an anti-aliasing filter.

10. The method of claim 1 , further comprising compressive sensing processing an analog input signal to generate a series of analog signal input values, and processing the analog signal input values using the programmable filter.

11. A method for mapping input values to capacitor values to implement a programmable discrete time analog filter, comprising:
accepting a plurality of filter coefficient input values;
determining a plurality of digital configuration values for a plurality of configurable capacitors in the programmable analog frequency domain filter, wherein the plurality of digital configuration values are determined according to a non-linear mapping of the filter coefficient input values; and
providing the digital configuration values for configuration of the programmable filter.

12. The method of claim 11 , further comprising determining an analog Discrete Fourier Transform of an input signal.

13. The method of claim 11 , further comprising providing a passive signal scaling circuit.

14. The method of claim 11 , wherein the filter coefficient input values are floating point numbers and the non-linear mapping comprises mapping the floating point numbers to DAC values.

15. The method of claim 11 , wherein each of the digital configuration values is for configuring capacitance of a capacitive element of the plurality of configurable capacitors.

16. The method of claim 11 , further comprising providing at least one charge sharing stage wherein at least a subset of the plurality of configurable capacitors share charges.

17. A programmable discrete time analog filter, comprising:
an input for accepting a series of analog signal input values;
a plurality of analog storage elements configurable to store the series of signal input values;
a plurality of passive signal scaling circuits, each including a plurality of configurable capacitors, wherein each of the plurality of passive signal scaling circuits is configurable to accept one of the analog signal input values from one of the analog storage elements and store an analog representation of a scaled signal value; and
means for accepting a plurality of filter coefficient input values and determining a plurality of digital configuration values for the plurality of configurable capacitors, wherein the plurality of digital configuration values are determined according to a non-linear mapping of the filter coefficient input value.

18. The programmable discrete time analog filter of claim 17 , wherein the filter coefficient input values are floating point numbers and the non-linear mapping comprises mapping the floating point numbers to DAC values.

19. The programmable discrete time analog filter of claim 17 , further comprising a passive combination circuit for forming an analog output signal value, wherein forming the analog output signal value includes combining the stored analog representation of the scaled signal value for a plurality of analog input signal values.

20. The programmable discrete time analog filter of claim 17 , further comprising a processor for performing compressive sensing of an analog input signal to generate the series of analog signal input values.

Assignees

• Analog Devices Inc

Inventors

• Nestler Eric
• Zlatkovic Vladimir
• Venuti Jeffrey

Classifications

• H04R25/00

  Electric hearing aids · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03H7/0138 Primary

  Electrical filters or coupling circuits · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• G10K15/00

  Acoustics not otherwise provided for · CPC title