Active regions with compatible dielectric layers

Patent metadata

Field	Value
Publication number	US-9847420-B2
Application number	US-201715473503-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Sep 18, 2006
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a substrate comprising a first semiconductor material;
a first isolation region and a second isolation region in the substrate, wherein a portion of the first semiconductor material of the substrate is laterally between the first isolation region and the second isolation region;
a trench in the portion of the first semiconductor material of the substrate, the trench laterally between the first isolation region and the second isolation region, the trench having a first sidewall that tapers inwardly from a top of the first isolation region to a bottom of the trench, and the trench having a second sidewall that tapers inwardly from a top of the second isolation region to the bottom of the trench;
a region comprising a second semiconductor material in the trench, the second semiconductor material different than the first semiconductor material, wherein the region comprising the second semiconductor material is discrete from the portion of the first semiconductor material of the substrate laterally between the first isolation region and the second isolation region;
a gate dielectric on a portion of the region comprising the second semiconductor material;
a gate electrode on the gate dielectric, the gate electrode comprising a metal, and the gate electrode having a first sidewall and a second sidewall;
a first dielectric spacer laterally adjacent the first sidewall of the gate electrode;
a second dielectric spacer laterally adjacent the second sidewall of the gate electrode;
a source region at the first sidewall of the gate electrode; and
a drain region at the second sidewall of the gate electrode, wherein the source region and the drain region are in recesses in the region comprising the second semiconductor material, the source region and the drain region comprising a third semiconductor material different from the second semiconductor material.

2. The integrated circuit structure of claim 1 , wherein the source region and the drain region are in the region comprising the second semiconductor material.

3. The integrated circuit structure of claim 1 , wherein the source region is a raised source region and the drain region is a raised drain region, and wherein an uppermost surface of the raised source region and the raised drain region is above an uppermost surface of the region comprising the second semiconductor material.

4. The integrated circuit structure of claim 1 , wherein the source region and the drain region have a lattice constant different than a lattice constant of the region comprising the second semiconductor material.

5. The integrated circuit structure of claim 1 , wherein the gate dielectric comprises a first gate dielectric layer directly on the portion of the region comprising the second
semiconductor material, and wherein the gate dielectric comprises a second gate dielectric layer having a first portion on the first gate dielectric layer, the second gate dielectric layer discrete from the first gate dielectric layer.

6. The integrated circuit structure of claim 5 , wherein the first gate dielectric layer comprises silicon and oxygen, and wherein the second gate dielectric layer comprises hafnium and oxygen.

7. The integrated circuit structure of claim 5 , wherein the second gate dielectric layer comprises a second portion along the first sidewall of the gate electrode, and a third portion along the second sidewall of the gate electrode, wherein the first dielectric spacer laterally is adjacent the second portion of the second gate dielectric layer along the first sidewall of the gate electrode, and wherein the second dielectric spacer is laterally adjacent the third portion of the second gate dielectric layer along the second sidewall of the gate electrode.

8. The integrated circuit structure of claim 1 , wherein the first isolation region and the second isolation region extend to a depth in the substrate below a bottommost surface of the region comprising the second semiconductor material.

9. The integrated circuit structure of claim 1 , further comprising:
a first tip region in the region comprising the second semiconductor material at the first side of the gate electrode; and
a second tip region in the region comprising the second semiconductor material at the second side of the gate electrode.

10. The integrated circuit structure of claim 1 , wherein the first semiconductor material is silicon.

11. The integrated circuit structure of claim 10 , wherein the second semiconductor material is germanium.

12. The integrated circuit structure of claim 10 , wherein the second semiconductor material is a group III-V material.

13. An integrated circuit structure, comprising:
a semiconductor fin above a substrate, the semiconductor fin having an upper fin portion on a lower fin portion, the lower fin portion comprising a first semiconductor material and the upper fin portion comprising a second semiconductor material different from the first semiconductor material, and the lower fin portion discrete from the upper fin portion with an interface between the lower fin portion and the upper fin portion;
a first isolation region at a first side of the semiconductor fin, wherein the first isolation region has an upper surface substantially co-planar with the interface between the lower fin portion and the upper fin portion;
a second isolation region at a second side of the semiconductor fin opposite the first side, wherein the second isolation region has an upper surface substantially co-planar with the interface between the lower fin portion and the upper fin portion;
a gate dielectric on a top and sidewalls of a portion of the upper fin portion;

a gate electrode on the gate dielectric, the gate electrode comprising a metal, and the gate electrode having a first sidewall and a second sidewall;
a first dielectric spacer laterally adjacent the first sidewall of the gate electrode; a second dielectric spacer laterally adjacent the second sidewall of the gate electrode;
a source region at the first sidewall of the gate electrode;

a drain region at the second sidewall of the gate electrode; and
a channel region in the upper fin portion between the source region and the drain region.

14. The integrated circuit structure of claim 13 , wherein the gate dielectric comprises a first gate dielectric layer directly on the portion of the upper fin portion, and wherein the gate dielectric comprises a second gate dielectric layer having a first portion on the first gate dielectric layer, the second gate dielectric layer discrete from the first gate dielectric layer.

15. The integrated circuit structure of claim 14 , wherein the first gate dielectric layer comprises silicon and oxygen, and wherein the second gate dielectric layer comprises hafnium and oxygen.

16. The integrated circuit structure of claim 14 , wherein the second gate dielectric layer comprises a second portion along the first sidewall of the gate electrode, and a third portion along the second sidewall of the gate electrode, wherein the first dielectric spacer
laterally is adjacent the second portion of the second gate dielectric layer along the first sidewall of the gate electrode, and wherein the second dielectric spacer is laterally adjacent the third portion of the second gate dielectric layer along the second sidewall of the gate electrode.

17. The integrated circuit structure of claim 13 , wherein the first semiconductor material is silicon.

18. The integrated circuit structure of claim 17 , wherein the se

Assignees

• Intel Corp

Inventors

• Ranade Pushkar

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P14/69398

  the material having a perovskite structure, e.g. BaTiO3 · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title