Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices

Patent metadata

Field	Value
Publication number	US-9847340-B2
Application number	US-201414227217-A
Country	US
Kind code	B2
Filing date	Mar 27, 2014
Priority date	Mar 27, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

First claim

What is claimed is:

1. A 3D NAND memory structure comprising:
a control gate and a floating gate disposed between a first insulating layer and a second insulating layer;
an interpoly dielectric (IPD) layer disposed between the control gate and the floating gate such that the IPD layer electrically isolates the control gate from the floating gate; and
a tunnel dielectric layer disposed on the floating gate opposite the control gate, wherein the floating gate comprises an oxidized portion along an interface with the tunnel dielectric layer.

2. The memory structure of claim 1 , wherein the portion of the floating gate that is oxidized is about 10 angstroms or less beyond the tunnel dielectric layer interface.

3. The memory structure of claim 1 , wherein the floating gate is substantially free of curved interfaces.

4. The memory structure of claim 1 , wherein an interface between the floating gate and tunnel dielectric layer is substantially flat.

5. The memory structure of claim 1 , wherein the floating gate has a size that is substantially the same as a size prior to creation of the tunnel dielectric layer.

6. The memory structure of claim 1 , wherein the tunnel dielectric layer is substantially free of dopant contamination from the floating gate.

7. The memory structure of claim 1 , wherein the floating gate has a substantially uniform dopant distribution.

8. The memory structure of claim 1 , wherein the floating gate has a shape that is substantially the same as a shape prior to creation of the tunnel dielectric layer.

9. The memory structure of claim 1 , wherein the floating gate has a height at an interface with the tunnel dielectric layer that is substantially the same as a height at an interface with the IPD layer.

10. A method of forming a tunnel dielectric layer in a 3D NAND memory structure comprising:
depositing a layer of material on an exposed surface of a floating gate in a cell stack substrate;
over-oxidizing the layer of material to form the tunnel dielectric layer while also
oxidizing a portion of the floating gate along an interface with the tunnel dielectric layer.

11. The method of claim 10 , wherein the material is deposited at a thickness sufficient to operate as a tunnel dielectric layer.

12. The method of claim 11 , wherein the thickness is from about 50-80 angstroms.

13. The method of claim 10 , wherein the material is a member selected from the group consisting of polysilicon and silicon nitride.

14. The method of claim 10 , wherein the material is deposited at a thickness sufficient to operate as a tunnel dielectric layer following oxidation of the material.

15. The method of claim 10 , wherein the thickness of the deposited material is from about 25 angstroms to about 40 angstroms and the thickness of the tunnel dielectric layer is from about 50 angstroms to about 80 angstroms.

16. The method of claim 10 , wherein over-oxidizing the material to form the tunnel dielectric layer comprises:
oxidizing a portion of the material in the layer;
removing the oxidized portion of the material in the layer; and
oxidizing the remaining material in the layer.

17. The method of claim 16 , wherein the thickness of the deposited material is from about 60 angstroms to about 70 angstroms and the thickness of the tunnel dielectric layer is from about 50 angstroms to about 80 angstroms.

18. The method of claim 10 , wherein the portion of the floating gate that is oxidized is about 10 angstroms or less beyond the tunnel dielectric layer interface.

19. The method of claim 18 , wherein the floating gate is substantially flush with an exposed surface of the cell stack substrate at the time the layer is deposited.

20. The method of claim 10 , wherein the material does not function as a tunnel dielectric before the oxidizing.

Assignees

• Fan Darwin
• Koka Sateesh
• Haller Gordon
• Hopkins John
• Surthi Shyam
• Khandekar Anish
• Intel Corp

Inventors

• Fan Darwin
• Koka Sateesh
• Haller Gordon
• Hopkins John
• Surthi Shyam
• Khandekar Anish

Classifications

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/30

  characterised by the memory core region · CPC title