Nonvolatile semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9287388-B2
Application number	US-201313780150-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Apr 10, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similally to the plurality of first memory cells.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising:
a memory string having a plurality of memory cells electrically connected in series, the memory cells being stacked in a first direction, the memory string including,
a first semiconductor body extending in the first direction,
a plurality of first floating electrodes provided on a side surface of the first semiconductor body via a first insulating layer, the first floating electrodes being stacked in the first direction, and

a plurality of first conductive layers stacked in the first direction, one of the first conductive layers being provided on a side surface of one of the first floating electrodes via a second insulating layer,
the first conductive layers and the first floating electrodes including one of W, Ta, Ti, and Mo,
a thickness of one of the first conductive layers being the same as a thickness of one of the first floating electrodes provided beside the one of the first conductive layers.

2. The device according to claim 1 , wherein the memory string further includes,
a second semiconductor body provided beside the first semiconductor body, the second semiconductor body extending in the first direction,
a plurality of second floating electrodes provided on a side surface of the second semiconductor body via a third insulating layer, the second floating electrodes being stacked in the first direction,
a plurality of second conductive layers stacked in the first direction, one of the second conductive layers being provided on a side surface of one of the second floating electrodes via a fourth insulating layer, and
a connection body connected to the first semiconductor body and the second semiconductor body,
the second conductive layers and the second floating electrodes including one of W, Ta, Ti, and Mo.

3. The device according to claim 2 , further comprising:
a first select transistor;
a second select transistor;
a bit line; and
a source line;
the first select transistor including,
a third semiconductor body extending in the first direction,
a first select gate electrode, and
the third semiconductor body having one end connected to the first semiconductor body and an other end connected to the bit line;

the second select transistor including,
a fourth semiconductor body extending in the first direction,
a second select gate electrode, and
the fourth semiconductor body having one end connected to the second semiconductor body and an other end connected to the source line.

4. The device according to claim 2 , wherein the connection body includes at least one of TaN, TiN, W, Mo, and Ta.

5. The device according to claim 2 , wherein the connection body includes conductive silicon.

6. The device according to claim 2 , wherein
a thickness of one of the second conductive layers is the same as a thickness of one of the second floating electrodes provided beside the one of the second conductive layers.

7. The device according to claim 1 , further comprising:
a first select transistor; and
a bit line;
the first select transistor including,
a third semiconductor body extending in the first direction,
a first select gate electrode, and
the third semiconductor body having one end connected to the first semiconductor body and an other end connected to the bit line.

8. The device according to claim 1 , wherein
materials of the first conductive layers are the same as materials of the first floating electrodes.

9. The device according to claim 1 , further comprising:
a plurality of first interlayer insulating films; and
a plurality of second interlayer insulating films, wherein
each of the first interlayer insulating films and each of the first floating electrodes are stacked alternately in the first direction,
each of the second interlayer insulating films and each of the first conductive layers are stacked alternately in the first direction,
a thickness of one of the first interlayer insulating films is the same as a thickness of one of the second interlayer insulating films provided beside the one of the first interlayer insulating films.

10. The device according to claim 9 , wherein
one of the first floating electrodes is provided between adjacent ones of the first interlayer insulating films in the first direction, the one of the first floating electrodes being in contact with the adjacent ones of the first interlayer insulating film.

11. The device according to claim 1 , wherein
the first insulating layer is not connected to the second insulating layer.

12. A nonvolatile semiconductor memory device comprising:
a memory string having a plurality of memory cells electrically connected in series, the memory cells being stacked in a first direction, the memory string including,
a first semiconductor body extending in the first direction,
a plurality of first floating electrodes provided on a side surface of the first semiconductor body via a first insulating layer, the first floating electrodes being stacked in the first direction,
a plurality of first conductive layers stacked in the first direction, one of the first conductive layers being provided on a side surface of one of the first floating electrodes via a second insulating layer,

the first floating electrodes including a material of a work function larger than a work function of the first conductive layers, and
the first conductive layers including silicon containing an n-type impurity and the first floating electrodes including silicon containing a p-type impurity.

13. The device according to claim 12 , wherein the memory string further includes,
a second semiconductor body provided beside the first semiconductor body, the second semiconductor body extending in the first direction,
a plurality of second floating electrodes provided on a side surface of the second semiconductor body via a third insulating layer, the second floating electrodes being stacked in the first direction,
a plurality of second conductive layers stacked in the first direction, one of the second conductive layers being provided on a side surface of one of the second floating electrodes via a fourth insulating layer,
a connection body connected to the first semiconductor body and the second semiconductor body, and
the second floating electrodes including a material of a work function larger than a work function of the second conductive layers.

14. The device according to claim 13 , wherein the second conductive layers include silicon containing an n-type impurity and the second floating electrodes include silicon containing a p-type impurity.

15. The device according to claim 12 , further comprising:
a first select transistor; and
a bit line;
the first select transistor including,
a third semiconductor body extending in the first direction,
a first select gate electrode, and
the third semiconductor body having one end connected to the first semiconductor body and an other end connected to the bit line.

16. The device according to claim 13 , wherein the connection body includes at least one of TaN, TiN, W, Mo, and Ta.

17. The device according to claim 13 , wherein the connection body includes conductive silicon.

18. A nonvolatile semiconductor memory device comprising:
a memory string having a plurality of memory cells electrically connected in series, the memory cells being stacked in a first direction, the memory string including,
a first semiconductor body extending in the first direction,
a plurality of first floating electrodes provided on a side surf

Assignees

• Toshiba Kk

Inventors

• Sawa Keiichi

Classifications

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• H01L29/788

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic