Method of forming a junction field effect transistor

Patent metadata

Field	Value
Publication number	US-9847336-B2
Application number	US-201615245671-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Aug 24, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

First claim

What is claimed is:

1. A method of fabricating a junction field effect transistor (JFET), the method comprising:
providing a semiconductor substrate;
forming a well of a first dopant type in the substrate, wherein the well is isolated from the semiconductor substrate by an isolation region of a second dopant type that is the opposite of the first dopant type;
implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET;
implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET, wherein the gate is entirely formed within the well of the first dopant type;
prior to implanting the dopant of the first type and the dopant of the second type, patterning a pre-metal dielectric (PMD) layer on the well to form openings in the PMD layer at regions corresponding to the source, the drain and the gate, wherein the PMD layer permanently remains over a region corresponding to the channel and has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer; and
after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

2. The method according to claim 1 , wherein the thickness of the PMD layer is chosen as a function of a gate voltage at which the JFET is configured to be in a substantially off state.

3. The method according to claim 1 , further comprising forming one or more additional wells of the first dopant type, wherein the one or more additional wells are isolated from the substrate by a second isolation region of the second dopant type, and wherein the one or more additional wells are formed simultaneously with the well in which the JFET is formed, and wherein additional devices are formed in the one or more additional wells, together with the JFET, in a single process sequence.

4. The method according to claim 3 , wherein the additional devices comprise at least a surface diode.

5. The method according claim 1 , wherein four lithographic masks are used consecutively for fabricating the JFET, wherein the four lithographic masks comprise:
a first mask suitable for patterning a first resist mask on the substrate for defining an exposed area in which the well is formed;
a second mask suitable for patterning a second resist mask on the PMD layer for defining exposed areas in which the contact openings are formed;
a third mask suitable for patterning a third resist mask for exposing an area comprising a source area, a drain area and a portion of the PMD layer that covers a channel area for implanting dopants of the second type in the exposed area; and
a fourth mask suitable for patterning a fourth resist mask for exposing a gate area, for implanting dopants of the first type in the gate area.

6. The method according to claim 1 , wherein the semiconductor substrate is an interposer substrate.

7. The method according to claim 1 , wherein forming the well that is isolated from the substrate by the isolation region comprises:
forming a mask layer on the substrate while leaving an area of the substrate exposed;
implanting the exposed area with a dopant of the second type at a tilted angle with respect to a major surface of the substrate, thereby creating a buried well of the second dopant type; and
implanting the exposed area with a dopant of the first dopant type, thereby creating the well of the first dopant type that is isolated from the substrate by the buried well.

8. The method according to claim 7 , wherein two wells of the first dopant type isolated from the semiconductor substrate are created adjacent to each other by forming the mask layer in such a way that the mask layer leaves two adjacent areas of the substrate exposed, wherein:
the two adjacent areas are simultaneously implanted with a dopant of the second dopant type at the tilted angle, such that a well of the second dopant type is formed between the two adjacent areas by a merger of the buried wells;
the two adjacent areas are simultaneously implanted with a dopant of the first dopant type such that two adjacent wells of the first dopant type are formed;
a JFET is formed according to the method of claim 1 in at least one of the adjacent wells of the first dopant type; and
a complementary JFET is formed in the well of the second dopant type and complementary to the JFET, wherein the complementary JFET is formed together with the JFET in the two adjacent wells of the first doping type in a single process sequence.

9. The method according to claim 7 , wherein two adjacent wells of the first dopant type are formed by forming the mask layer in such a way that the mask layer leaves two adjacent areas of the semiconductor substrate exposed, and wherein the mask layer is further formed in such a way that it leaves an additional area of the substrate exposed, and wherein:
the two adjacent areas and the additional area are simultaneously implanted with a dopant of the second dopant type at the tilted angle, such that a well of the second dopant type is formed between the two adjacent areas, formed by a merger of the buried wells formed under surfaces of the adjacent areas, and such that a buried well of the second dopant type is formed under surfaces of the additional area that is isolated from the buried wells formed under the surfaces the adjacent areas;
the two adjacent areas and the additional area are simultaneously implanted with the dopant of the first type such that two adjacent wells of the first dopant type are formed, and a separate well of the first dopant type is formed in the isolated buried well;
a JFET is formed according to the method of claim 1 in the separate well of the first dopant type; and
an additional JFET formed in the well of the second dopant type, the additional JFET being complementary to the JFET, the complementary JFET being formed together with the JFET in the separate well of the first dopant type in a single process sequence.

10. A semiconductor device, comprising:
a substrate;
a first well of a first dopant type formed in the substrate, wherein the first well is isolated from the substrate by an isolation region of a second dopant type that is the opposite of the first dopant type, wherein the first well comprises a junction field effect transistor (JFET) formed therein,
wherein the JFET comprises:
a source, a drain and a channel each doped with a dopant of the second dopant type, the channel extending between the source and the drain,
a gate doped with a dopant of the first dopant type,
wherein the gate is entirely formed within the first well,
metal contacts formed on each of the source, the drain and the gate, and
a pre-metal dielectric (PMD) layer formed on the channel,
wherein doping profiles in the source and the drain are substantially the same, while a doping profile in the channel is shallower than the doping profiles in the source and the drain.

11. The semiconductor device according to claim 10 , wherein the first well is isolated from the substrate by a buried well of the second dopant type.

12. The semiconductor device according to claim 11 , further comprising a second well of the first dopant type, wherein the second well is isolated from the substrate by a buried well of the second dopant type, wherein the second well is formed adjacent the first well and separated from the first well by a well of the second dopant type, the well of the second doping type comprising a complementary JFET complementary to the JFET in the first well, the complementary

Assignees

• Imec Vzw

Inventors

• Hellings Geert
• Van Der Plas Geert
• Scholz Mirko

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title