Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9847300-B2
Application number	US-201615144917-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	Jul 13, 2012
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a plurality of substrates each including a plurality of chip mounting portions and external terminal forming portions;
(b) in each of the substrates, mounting a semiconductor chip on each of the chip mounting portions;
(c) after the step (b), in each of the substrates, electrically coupling a bonding pad of the semiconductor chip and the external terminal forming portion with a conductive component;
(d) after the step (c), in each of the substrates, sealing the semiconductor chip and the conductive component with a resin sealing body;
(e) after the step (d), in each of the substrates, forming a mark including product information on a surface of the resin sealing body;
(f) after the step (e), in each of the substrates, forming a plated layer on a surface of the external terminal forming portion exposed to an outside of the resin sealing body;
(g) after the step (f), in each of the substrates, singulating the substrate into a plurality of semiconductor devices by cutting the resin sealing body and the external terminal forming portion;
(h) after the step (g), in each of the semiconductor devices, carrying out a testing for screening a characteristic defect of the semiconductor chip sealed with the resin sealing body;
(i) after the step (h), in each of the semiconductor devices, carrying out a visual inspection for screening a visual defect; and
(j) among the semiconductor devices, shipping the semiconductor device determined to be nondefective in the step (i),
wherein unique identification information is attached to each of the substrate, the chip mounting portion of the substrate, the semiconductor chip, and a rack for storing and transporting the substrate,
wherein in each of the step (b) and the subsequent steps, a manufacturing history of each of the steps and the identification information are associated with each other via a server, thereby process control of the semiconductor devices is performed, and
wherein the process control is performed in a unit of rack up to the step (c), while on and after the step (d), the process control is performed in a unit of lot.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the identification information attached to the semiconductor chip includes a semiconductor wafer number, a diffusion lot number, positional information regarding the semiconductor chip in a semiconductor wafer, and nondefective product/defective product information regarding the semiconductor chip that are wafer process information regarding the semiconductor chip.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein a same diffusion lot number is attached to a plurality of the semiconductor chips manufactured in a same diffusion process, the diffusion lot number and identification information of the rack are associated with each other, and thereby process control of the semiconductor devices is performed.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein each piece of the identification information is formed in a form of a two-dimensional code.

5. The method of manufacturing a semiconductor device according to claim 4 , wherein the two-dimensional codes are marked by a laser beam, respectively.

Assignees

• Renesas Electronics Corp

Inventors

• Sakai Nobutaka
• Otake Mamoru
• Saito Koji
• Takahashi Tomishi

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title