Memristor programming error reduction

Patent metadata

Field	Value
Publication number	US-9847129-B2
Application number	US-201415324685-A
Country	US
Kind code	B2
Filing date	Jul 28, 2014
Priority date	Jul 28, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance. The error-corrected target resistance is a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor. The n-th switched memristor programming is to reduce a total resistance error of the switched memristor array.

First claim

What is claimed is:

1. A method of error reduction in memristor programming, the method comprising:
programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance, the error-corrected target resistance being a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor, where n is a positive integer ranging from one to N, and N is an integer greater than one;
programming a first switched memristor with a target resistance prior to programming the n-th switched memristor of the switched memristor array; and
measuring the resistance error of the switched memristor array prior to programming the n-th switched memristor,
wherein n excludes one; and
wherein the switched memristor array comprises N switched memristors, each switched memristor comprising a switch connected in parallel with a memristor, and wherein programming the n-th switched memristor reduces a total resistance error of a programmed resistance of the switched memristor array.

2. The method of error reduction in memristor programming of claim 1 , wherein the function of the resistance error and the target resistance comprises noise shaping using the resistance error.

3. The method of error reduction in memristor programming of claim 2 , wherein the switched memristor array comprises the N switched memristors connected in series, and wherein the noise shaping comprises first-order difference noise shaping, the error-corrected target resistance R n C of the n-th switched memristor being given by
R n C =R n T −R n−1 E

where R n T is the target resistance of the n-th switched memristor and R n−1 E is the resistance error of the switched memristor array prior to programming the n-th switched memristor.

4. The method of error reduction in memristor programming of claim 2 , wherein the switched memristor array comprises the N switched memristors connected in series, and wherein the noise shaping comprises second-order difference noise shaping, the error-corrected target resistance R n C of the n-th switched memristor being given by
R n C =R n T −2 R n−1 E +R n−2 E

where R n T is the target resistance of the n-th switched memristor, R n−1 E is the resistance error of the switched memristor array prior to programming the n-th switched memristor, and R n−2 E is the resistance error of the switched memristor array prior to programming the (n−1)-th switched memristor.

5. The method of error reduction in memristor programming of claim 1 , wherein the resistance error of the switched memristor array is an error in a programmed resistance of an (n−1)-th switched memristor.

6. The method of error reduction in memristor programming of claim 1 , wherein the resistance error of the switched memristor array is a total error in programmed resistances of all of the switched memristors of the switched memristor array except the n-th switched memristor.

7. A non-transitory computer readable medium including instructions that, when executed by a processor, implement the error reduction in memristor programming of claim 1 .

8. A non-transitory computer readable medium including instructions that, when executed by a processor, implement memristor programming error reduction comprising:
programming a first switched memristor of a switched memristor array with a target resistance;
measuring a resistance error of the switched memristor array; and
programming an n-th switched memristor of the switched memristor array with an error-corrected target resistance, the error-corrected target resistance comprising noise shaping using the measured resistance error, the noise shaping comprising one of first-order difference noise shaping and second-order difference noise shaping,
wherein the switched memristor array comprises N switched memristors connected in series, where n is an integer ranging from two to N and N is an integer greater than one, and wherein programming the n-th switched memristor reduces a total resistance error of a programmed resistance of the switched memristor array.

9. The non-transitory computer readable medium of claim 8 , wherein measuring a resistance error of the switched memristor array comprises measuring a resistance error in a programmed resistance of an (n−1)-th switched memristor.

10. An error reduction programmable switched memristor system comprising:
a switched memristor array having N switched memristors connected together to provide a programmable resistance; and
a memristor programmer to store analog data in the programmable resistance of the switched memristor array, the analog data is to be stored comprising programming an n-th switched memristor of the switched memristor array with an error-corrected target resistance, the error-corrected target resistance being a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor, where n is an integer ranging from one to N,
wherein target resistances of the N switched memristors represent the analog data, and wherein programming the n-th switched memristor is to reduce a total resistance error of the switched memristor array.

11. The error reduction programmable switched memristor system of claim 10 , wherein the function of the resistance error and the target resistance comprises noise shaping using the resistance error, wherein the noise shaping comprises one of first-order difference noise shaping and second-order difference noise shaping.

12. The error reduction programmable switched memristor system of claim 10 , wherein a switched memristor of the switched memristor array comprises a switch connected in parallel with a memristor, the switch being a field effect transistor (FET) with a source of the FET connected to a first terminal of the memristor and a drain of the FET connected to a second terminal of the memristor.

13. The error reduction programmable switched memristor system of claim 10 , further comprising:
a resistance measurement apparatus to measure the resistance error of the switched memristor array, the resistance error being an error in a programmed resistance of an (n−1)-th switched memristor,
wherein the memristor programmer comprises:
a processor;
a memory; and
a computer program stored in the memory, the computer program including instructions that, when executed by the processor, implement the storing of the analog data in the programmable resistance of the switched memristor array.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Buchanan Brent

Classifications

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title