Systems and methods for modeling memory access behavior and memory traffic timing behavior

Patent metadata

Field	Value
Publication number	US-9846627-B2
Application number	US-201615044044-A
Country	US
Kind code	B2
Filing date	Feb 15, 2016
Priority date	Feb 13, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Systems and methods for modeling memory access behavior and memory traffic timing behavior are disclosed. According to an aspect, a method includes receiving data indicative of memory access behavior resulting from instructions executed on a processor. The method also includes determining a statistical profile of the memory access behavior, the profile including tuple statistics of memory access behavior. Further, the method includes generating a clone of the executed instructions based on the statistical profile for use in simulating the memory access behavior.

First claim

What is claimed:

1. A method comprising:
receiving data indicative of a memory access behavior that results from instructions executed on a process, wherein the data are address stream values comprising an address tuple;
determining at least one of a stride tuple statistical profile and an address tuple statistical profile of the memory access behavior based on the received data; and
generating a clone of the data based on the at least one of the stride tuple statistical profile and the address tuple statistical profile in order to mimic the memory access behavior;
wherein determining a stride tuple statistical profile of the memory access behavior comprises:
calculating a difference between consecutive address stream values, wherein the calculation occurs between a consecutive initial address stream value and a subsequent address stream value;
repeating the difference calculation between the subsequent address stream value and a next consecutive address stream value until a last address stream value is reached;
determining a probability of a stride tuple transition from a first stride tuple to a second stride tuple; and
repeating the probability determination between a subsequent stride tuple value and a next consecutive stride tuple value until a last stride tuple value is reached.

2. The method of claim 1 , wherein the address tuple has a length of N≧0.

3. The method of claim 1 , wherein determining a probability of stride tuple transition comprises dividing the number of occurrences of the second stride tuple by the number of occurrences of the first stride tuple.

4. The method of claim 1 , wherein the stride tuple has a length of N≧1.

5. The method of claim 1 , wherein generating a clone of the data comprises generating a synthetic memory access stream including randomly-generated addresses based on the at least one of the stride tuple statistical profile and the address tuple statistical profile.

6. The method of claim 1 , wherein the stride tuple statistical profile comprises a stride history table that displays at least one of a previous stride and predicts at least one of a next stride.

7. The method of claim 6 , wherein the stride tuple statistical profile comprises a stack distance probability table.

8. The method of claim 6 , further comprising generating a binary clone based on the stride tuple statistical profile.

9. A method comprising:
receiving data indicative of a memory access behavior that results from instructions executed on a processor and cache hierarchy;
determining a statistical profile of the memory access behavior, wherein the statistical profile indicates feedback loop timing information of the memory access behavior and wherein the determination comprises:
categorizing memory access instructions into instructions that depend on a first traffic-generating instruction and that do not depend on the first traffic-generating instruction;
computing, for each dependency between instructions, an instruction count between a dependent instruction and an instruction upon which the dependent instruction depends; and
creating the statistical profile based on the number of categorized memory access instructions and the computed instruction count; and

generating a clone of the executed instructions based on the statistical profile for use in simulating the memory access behavior.

10. The method of claim 9 , wherein the data indicates memory requests to a memory subsystem.

11. The method of claim 10 , wherein the data indicates one or more of a read request and a write request to the memory subsystem.

12. The method of claim 11 , wherein the data indicates one or more of a read request and a write request to the memory subsystem and produced by a last level cache (LLC).

13. The method of claim 10 , wherein the data indicates a stack position distance for each of the memory requests to the memory subsystem.

14. The method of claim 10 , wherein the data indicates write backs associated with dirty blocks in the memory subsystem.

15. The method of claim 9 , wherein determining a statistical profile comprises determining a number of instructions that separate memory requests based on the received data.

16. The method of claim 15 , wherein the number of instructions indicates the number of instructions separating two consecutive memory requests.

17. The method of claim 9 , wherein the statistical profile comprises a stack distance profile probability for a plurality of stack positions in a memory subsystem.

18. The method of claim 9 , wherein the statistical profile comprises a probability of write to clean block for a plurality of stack positions in a memory subsystem.

19. The method of claim 9 , wherein the statistical profile comprises information about a number of last level cache (LLC) blocks that are dirty.

20. The method of claim 9 , wherein the statistical profile comprises information about a number of memory requests that are write backs.

21. The method of claim 9 , wherein the statistical profile comprises a recurrence probability of instructions that separate memory requests by a predetermined number of instruction counts.

22. The method of claim 9 , wherein the statistical profile comprises a probability of a next memory request being to the same memory region of a predetermined size as a current memory request.

23. The method of claim 9 , wherein the statistical profile comprises information about a number of occurrences of a predetermined distance over dependent instructions.

24. The method of claim 9 , wherein the statistical profile comprises a probability of a pair of traffic-generating instructions having a true dependence relation.

25. The method of claim 9 , wherein the statistical profile comprises information about a number of traffic-generating instructions having a dependent relation.

26. The method of claim 9 , wherein generating a clone comprises generating the clone stochastically based on the statistical profile.

Assignees

• Univ North Carolina State

Inventors

• Solihin Yan
• Wang Yipeng
• Awad Amro

Classifications

• G06F11/3037 Primary

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/3452

  Performance evaluation by statistical analysis · CPC title

• G06F11/3447

  Performance evaluation by modeling · CPC title

• G06F11/3461

  Trace driven simulation · CPC title

• G06F11/3428

  Benchmarking · CPC title