Flash memory controller, data processing system with flash memory controller and method of operating a flash memory controller

Patent metadata

Field	Value
Publication number	US-9720797-B2
Application number	US-201514755010-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

First claim

The invention claimed is:

1. A flash memory controller, comprising:
a system bus interface arranged to interface data communication between the flash memory controller and a system bus of a data processing system;
a debug bus interface arranged to interface data communication between the flash memory controller and a debug bus of the data processing system;
a flash access control block arranged to receive data access requests via the system bus interface and to perform storage I/O, input/output, operations on a flash memory array in response to the received data access requests;
a debug control block comprising a trace control block and arranged to monitor debug related information via the debug bus interface; and
storage resources including a random access memory;
wherein the flash memory controller is configured to selectively operate in one of storage operating mode and debug operating mode;
in the debug operating mode:
the flash access control block is configured to serve only read data access requests received via the system bus interface, and
the trace control block is configured to store trace messages in an allocated part of the storage resources in response to trace events, wherein the trace messages are generated on the basis of the monitored debug related information collected by the trace control block.

2. The flash memory controller according to claim 1 , further comprising:
an allocation/deallocation block configured to allocate at least a part of the storage resources on transitioning to the debug operating mode.

3. The flash memory controller according to claim 2 ,
wherein the storage resources further include registers of the flash memory controller,
wherein the allocation/deallocation block is further configured to reconfigure at least a part of registers of the flash memory controller on allocating at least a part of the storage resources;
wherein the trace control block is further configured to use the reconfigured registers as trace control and status registers.

4. The flash memory controller according to claim 3 ,
wherein the trace control block is further configured to perform one of starting and stopping one or more of a data trace, an ownership trace, a program trace and a watchpoint trace.

5. The flash memory controller according to claim 1 ,
wherein the trace control block is further arranged to deallocate the allocated part of the storage resources on transitioning to the storage operating mode.

6. The flash memory controller according to claim 1 ,
wherein the flash memory controller is further configured to selectively operate in halt operating mode;
wherein on occurrence of a breakpoint signaled to the flash memory controller, the flash memory controller is configured to transition to the halt operating mode;
in the halt operating mode:
the trace control block is configured to serve trace message retrieval requests received from an external debugger.

7. The flash memory controller according to claim 1 ,
wherein the debug related information comprises data, instruction and address information, wherein the trace control block is further configured to snoop the data, instruction and addresses on an internal processor core bus through the debug bus interface and the debug bus of the data processing system.

8. The flash memory controller according to claim 7 ,
wherein the trace control block is further arranged to perform monitoring related to at least one of a trace of a processor, bus and peripheral.

9. The flash memory controller according to claim 1 ,
in the debug operating mode:
the flash access control block is configured to control a transition of the flash memory controller to the storage operating mode in response to detecting a data access request.

10. The flash memory controller according to claim 1 , further comprising
a diagnostic control block configured to retrieve diagnostic information;
wherein the flash memory controller is further configured to selectively operate in diagnostic operating mode;
in the diagnostic operating mode:
the flash access control block is configured to serve only read data access requests received via the system bus interface, and
the diagnostic control block is configured to store diagnostic messages in an allocated part of the storage resources in response to diagnostic events, wherein the diagnostic messages are generated on the basis of the retrieved diagnostic information collected by the diagnostic control block.

11. The flash memory controller according to claim 10 , further comprising an allocation/deallocation block configured to allocate at least a part of the storage resources on transitioning to the diagnostic operating mode.

12. The flash memory controller according to claim 10 , further comprising
wherein the flash memory controller is further configured to selectively operate in capture operating mode;
wherein on occurrence of a system failure signaled to the flash memory controller, the flash memory controller is configured to transition to the capture operating mode;
in the capture operating mode:
the diagnostic control block is configured to program the stored diagnostic messages in the flash memory array.

13. The flash memory controller according to claim 1 , further comprising
a configurable controlling unit configured to operate one or more of the control blocks.

14. The flash memory controller according to claim 1 , further comprising at least one of:
a breakpoint/watchpoint control block configured
to generate a watchpoint triggering a trace event in response to detection of at least one of a program counter value, an address value, an address range, and a data value, and
to use reconfigured registers as comparator registers; and
a state sequencing control block configured to generate trigger events in response to a conditional state sequence.

15. The flash memory controller according to claim 1 ,
in the storage operating mode:
the flash access control block is configured to serve random data access requests received via the system bus interface.

16. An integrated processing system, comprising
at least one processor core;
a system bus;
a debug bus;
a flash memory array for storing instructions and data; and
a flash memory controller, coupled to the system bus and the debug bus, including;
a system bus interface arranged to interface data communication between the flash memory controller and the system bus of a data processing system;
a debug bus interface arranged to interface data communication between the flash memory controller and the debug bus of the integrated processing system;
a flash access control block arranged to receive data access requests via the system bus interface and to perform storage I/O, input/output, operations on the flash memory array in response to the received data access requests;
a debug control block comprising a trace control block and arranged to monitor debug related information via the debug bus interface; and
storage resources including a random access memory;
wherein the flash memory controller is configured to selectively operate in one of storage operating mode and debug operating mode;
in the debug operating mode:
the flash access control block is configured to serve only read data access requests received via the system bus interface, and
the trace control block is configured to store trace messages in an allocated part of the storage resources in response to trace events, wherein the trace messages are generated on the basis of the monitored debug related information collected by th

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Broderick Damon Peter
• Heisswolf Dirk
• Pachl Andreas Ralph

Classifications

• G06F11/3495 Primary

  for systems · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G01R31/319

  Tester hardware, i.e. output processing circuits · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G06F11/3656 Primary

  using a specific debug interface · CPC title