Method of forming a circuit for interconnecting electronic devices

Patent metadata

Field	Value
Publication number	US-9844148-B2
Application number	US-201615379177-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Sep 10, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Provided are interconnect circuits for interconnecting arrays of devices and methods of forming these interconnect circuits as well as connecting these circuits to the devices. An interconnect circuit may include a conductive layer and one or more insulating layers. The conductive layer may be patterned with openings defining contact pads, such that each pad is used for connecting to a different electrical terminal of the interconnected devices. In some embodiments, each contact pad is attached to the rest of the conductive layer by a fusible link formed from the same conductive layer as the contact pad. The fusible link controls the current flow to and from this contact pad. The insulating layer is laminated to the conductive layer and provides support to the contacts pads. The insulating layer may also be patterned with openings, which allow forming electrical connections between the contact pads and cell terminals through the insulating layer.

First claim

What is claimed is:

1. A method of forming a circuit for interconnecting electronic devices, the method comprising:
forming a set of conductive layer openings in a conductive layer,
wherein the conductive layer openings in the set are separated from each other by two or more connecting tabs,
wherein the set of the conductive layer openings and the two or more connecting tabs surround and define a region of the conductive layer, and
wherein, after forming the set of the conductive layer openings, the two or more connecting tabs mechanically support and maintain registration of the region of the conductive layer relative to other portions of the conductive layer;

laminating the conductive layer comprising the set of the conductive layer openings to a support layer,
wherein, after laminating the conductive layer to the support layer, the support layer mechanically supports and maintains registration of the region of the conductive layer relative to the other portions of the conductive layer; and

removing at least a first connecting tab of the two or more connecting tabs,
wherein removing at least the first connecting tab of the two or more connecting tabs converts the set of the conductive layer openings into a continuous conductive layer channel at least partially surrounding and defining the region of the conductive layer.

2. The method of claim 1 , wherein at least a second connecting tab of the two or more connecting tabs is retained while removing at least the first connecting tab of the two or more connecting tabs, and wherein at least the second connecting tab of the two or more connecting tabs interconnects the region of the conductive layer with the other portions of the conductive layer.

3. The method of claim 2 , wherein at least the second connecting tab of the two or more connecting tabs is operable as a fusible link and limits an electrical current level between the region of the conductive layer with the other portions of the conductive layer.

4. The method of claim 2 , wherein the continuous conductive channel ends at the second connecting tab of the two or more connecting tabs.

5. The method of claim 1 , wherein removing at least the first connecting tab of the two or more connecting tabs comprises removing all of the two or more connecting tabs.

6. The method of claim 1 , wherein removing at least the first connecting tab of the two or more connecting tabs also removes at least one support layer portion of the support layer laminated to at least the first connecting tab of the two or more connecting tabs.

7. The method of claim 1 , wherein the support layer is operable as a first insulating layer and remains a part of the interconnect circuit.

8. The method of claim 7 , wherein the support layer remains substantially intact while removing at least the first connecting tab of the two or more connecting tabs.

9. The method of claim 1 , further comprising:
after removing at least the first connecting tab of the two or more connecting tabs, laminating a first insulating layer to the conductive layer such that the conductive layer is disposed between the first insulating layer and the support layer; and
after laminating the first insulating layer to the conductive layer, removing the support layer from the conductive layer.

10. The method of claim 9 , wherein the first insulating layer comprises first insulating layer openings prior to laminating the first insulating layer to the conductive layer, and wherein the conductive layer openings provide aligning features for the first insulating layer openings during lamination of the first insulating layer to the conductive layer.

11. The method of claim 9 , wherein, prior to laminating the first insulating layer to the conductive layer, the first insulating layer comprises first insulating layer openings, and
wherein, after laminating the first insulating layer to the conductive layer, at least one of the insulating layer openings overlaps with the region of the conductive layer.

12. The method of claim 11 , wherein edges of the region of the conductive layer are supported by the first insulating layer.

13. The method of claim 9 , further comprising:
after removing the support layer from the conductive layer, laminating a second insulating layer to the conductive layer such that the conductive layer is disposed between the first insulating layer and the second insulating layer.

14. The method of claim 13 , wherein the first insulating layer comprises a first insulating layer opening, and wherein the second insulating layer comprises a second insulating layer opening partially overlapping with the first insulating layer opening.

15. The method of claim 13 , wherein at least one of the first insulating layer or the second insulating layer comprises an adhesive sublayer for attachment of the interconnect circuit to a heat sink, and wherein the adhesive sublayer is disposed on a surface of one of the first insulating layer or the second insulating layer opposite of the conductive layer.

16. The method of claim 1 , wherein the interconnect circuit is further bonded to a housing or heat sink.

17. The method of claim 1 , wherein the conductive layer comprises a base sublayer and a surface sublayer, wherein the base sublayer has a different composition than the surface sublayer.

18. The method of claim 17 , wherein the surface sublayer directly contacts at least one of a first insulating layer or a second insulating layer in the interconnect circuit or an adhesive layer disposed between the surface sublayer and the first insulating layer or the second insulating layer.

19. The method of claim 1 , wherein the region of the conductive layer is a voltage monitoring trace or an ancillary trace.

20. The method of claim 19 , wherein the voltage monitoring trace or the ancillary trace are monolithic with a conductive island comprising multiple contact pads.

Assignees

• Cellink Corp

Inventors

• Coakley Kevin
• Brown Malcolm

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H01M10/48

  Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte (constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569) · CPC title

• H01M50/516

  by welding, soldering or brazing · CPC title

• H01M50/522

  Inorganic material · CPC title