Interconnect for battery packs

Patent metadata

Field	Value
Publication number	US-9545010-B2
Application number	US-201514836946-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Sep 10, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Provided are interconnect circuits for interconnecting arrays of battery cells and methods of forming these interconnect circuits as well as connecting these circuits to the battery cells. An interconnect circuit may include a conductive layer and one or more insulating layers. The conductive layer may be patterned with openings defining contact pads, such that each pad is used for connecting to a different battery cell terminal. In some embodiments, each contact pad is attached to the rest of the conductive layer by a fusible link formed from the same conductive layer as the contact pad. The fusible link controls the current flow to and from this contact pad. The insulating layer is laminated to the conductive layer and provides support to the contacts pads. The insulating layer may also be patterned with openings, which allow forming electrical connections between the contact pads and cell terminals through the insulating layer.

First claim

What is claimed is:

1. An interconnect circuit for interconnecting an array of devices, the interconnect circuit comprising:
a conductive layer comprising conductive layer islands electrically isolated from each other,
wherein at least one of the conductive layer islands comprises a contact pad, a fusible link, and a conductive layer channel,
wherein the conductive layer channel partially surrounds and separates the contact pad from a remaining portion of the at least one of the conductive layer islands and terminates at the fusible link such that the fusible link provides an electrical connection between the contact pad and the remaining portion; and

an insulating layer laminated to the conductive layer
wherein the insulating layer mechanically supports and maintains registration of the conductive layer islands relative to each other, and
wherein the fusible link is freestanding and does not overlap with the insulating layer.

2. The interconnect circuit of claim 1 , wherein the fusible link is flexible and allows the contact pad to move relative to the remaining portion while the contact pad remains connected to the remaining portion.

3. The interconnect circuit of claim 2 , wherein the contact pad lies out of plane relative to the remaining portion.

4. The interconnect circuit of claim 1 , wherein the insulating layer comprises an insulating layer opening aligned with the contact pad and exposing the contact pad on both surfaces.

5. The interconnect circuit of claim 1 , wherein the conductive layer comprises aluminum and has a thickness of between 25 micrometers to 2 millimeters.

6. The interconnect circuit of claim 1 , where in the insulating layer comprises a material selected from the group polyimide (PI), polyethylene naphthalate (PEN), and polyethylene terephthalate (PET).

7. The interconnect circuit of claim 1 , wherein the insulating layer comprises polyethylene terephthalate (PET).

8. The interconnect circuit of claim 1 , wherein the insulating layer thickness is in the range 10 micrometers and 125 micrometers.

9. The interconnect circuit of claim 1 , further comprising a voltage monitoring trace electrically coupled to the at least one of the conductive layer islands.

10. The interconnect circuit of claim 1 , wherein the insulating layer comprises an adhesive sublayer.

11. The interconnect circuit of claim 10 , wherein the adhesive sublayer is adhered to the conductive layer.

12. The interconnect circuit of claim 10 , wherein the insulating layer further comprises an additional adhesive sublayer facing away from the conductive layer.

13. A battery pack assembly comprising:
an interconnect circuit comprising:
a conductive layer comprising conductive layer islands electrically isolated from each other,
wherein at least one of the conductive layer islands comprises a contact pad, a fusible link, and a conductive layer channel,
wherein the conductive layer channel partially surrounds and separates the contact pad from a remaining portion of the at least one of the conductive layer islands and terminates at the fusible link such that the fusible link provides an electrical connection between the contact pad and the remaining portion; and

an insulating layer laminated to the conductive layer,
wherein the insulating layer mechanically supports and maintains registration of the conductive layer islands relative to each other, and
wherein the fusible link is freestanding and does not overlap with the insulating layer; and

a group of battery cells interconnected by the interconnect circuit.

14. The battery pack assembly of claim 13 , wherein the battery cells in the group comprise cylindrical battery cells.

15. The battery pack assembly of claim 13 , wherein at least one of the battery cells in the group is welded to the contact pad of the at least one of the conductive layer islands.

16. The battery pack assembly of claim 13 , wherein the conductive layer of the interconnect circuit comprises a base sublayer and at least one surface sublayer having a different composition than the base sublayer.

17. The battery pack assembly of claim 16 , wherein the at least one surface sublayer is welded to at least one of the battery cells in the group.

18. The battery pack assembly of claim 17 , wherein the at least one surface sublayer welded to the at least one of the battery cells in the group comprises nickel.

19. The battery pack assembly of claim 16 , wherein the at least one surface sublayer faces away from the group of the battery cells and the base layer makes direct contact with at least one of the battery cells in the group.

20. The interconnect circuit of claim 16 , wherein the at least one surface sublayer faces away from the group of the battery cells and comprises copper.

Assignees

• Cellink Corp
• Cellink Corp

Inventors

• Coakley Kevin Michael
• Brown Malcolm

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H01M10/48

  Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte (constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569) · CPC title

• H01M50/516

  by welding, soldering or brazing · CPC title

• H01M50/522

  Inorganic material · CPC title