System and method for managing holdover

Patent metadata

Field	Value
Publication number	US-9843439-B2
Application number	US-201615007967-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Jan 27, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A system for managing holdover. The system may include a local oscillator device. The system may include a phase locked loop (PLL) device coupled to the local oscillator device and a reference clock source. The PLL device may obtain a reference clock signal from the reference clock source to produce an extracted clock signal. The system may include a drift monitoring device coupled to the local oscillator device and the PLL device. The drift monitoring device may determine an amount of oscillator drift within the local oscillator device using the extracted clock signal and an oscillator signal from the local oscillator device. The system may include a drift compensation device coupled to the drift monitoring device and the PLL device. The drift compensation device may transmit a drift compensation signal to the PLL device based on the amount of oscillator drift.

First claim

What is claimed is:

1. A system for managing holdover, comprising:
a local oscillator device;
a phase locked loop (PLL) device coupled to the local oscillator device and a first reference clock source, wherein the PLL device is configured to obtain a first reference clock signal from the first reference clock source to produce an extracted clock signal;
a drift monitoring device coupled to the local oscillator device and the PLL device, wherein the drift monitoring device is configured to determine an amount of oscillator drift within the local oscillator device using the extracted clock signal and an oscillator signal from the local oscillator device; and
a drift compensation device coupled to the drift monitoring device and the PLL device, wherein the drift compensation device is configured to transmit a drift compensation signal to the PLL device based on the amount of oscillator drift.

2. The system of claim 1 , further comprising:
a holdover monitoring device coupled to the drift monitoring device, wherein the holdover monitoring device is configured to transmit, to a computer device, a holdover alarm signal indicating the extracted clock signal is outside a desired timing specification.

3. The system of claim 2 ,
wherein the holdover monitoring device is configured to trigger the holdover alarm signal when a holdover alarm threshold expires, and
wherein the holdover alarm threshold corresponds to an amount of time before the extracted clock signal is outside the desired timing specification for the extracted clock signal.

4. The system of claim 1 , further comprising:
an error detector coupled to the PLL device and a second reference clock source,
wherein the error detector is configured to generate, using a second reference clock signal from the second reference clock source, a frequency error signal for the PLL device.

5. The system of claim 4 , further comprising:
a reference clock noise detector coupled to the second reference clock source and the drift monitoring device,
wherein the reference clock noise detector is configured to determine an amount of noise in the second reference clock signal, and
wherein the drift monitoring device is further configured to adjust, using the amount of noise, the amount of oscillator drift.

6. The system of claim 1 ,
wherein the first reference clock source is located on a master clock reference on a network,
wherein the first reference clock source is configured to transmit the first reference clock signal to the PLL device over a connection between the master clock reference and the PLL device over the network, and
wherein the drift compensation device is further configured to transmit the drift compensation signal to the PLL device after the connection is terminated.

7. The system of claim 1 ,
wherein the amount of oscillator drift corresponds to a shifting of an operating frequency of the local oscillator device resulting from temperature effects to the local oscillator device.

8. The system of claim 1 ,
wherein the local oscillator device is an oven-controlled crystal oscillator (OCXO).

9. A method for managing holdover, comprising:
obtaining an oscillator signal from a local oscillator device;
obtaining a first extracted clock signal from a phase locked loop (PLL) device;
determining, using the oscillator signal and the first extracted clock signal, an amount of oscillator drift for the local oscillator device;
detecting that a connection is terminated over a network between the PLL device and a master clock reference;
determining, in response to detecting that the connection is terminated and using the amount of oscillator drift, a drift compensation signal;
transmitting the drift compensation signal to the PLL device; and
generating, from the PLL device and using the drift compensation signal, a second extracted clock signal, wherein the drift compensation signal compensates the second extracted clock signal for the amount of oscillator drift.

10. The method of claim 9 , further comprising:
obtaining, at an error detector, a reference clock signal and the first extracted clock signal to generate a frequency error signal for the PLL device, wherein the frequency error signal compensates for frequency error in the first extracted clock signal;
determining an amount of noise in the reference clock signal; and
adjusting, using the amount of noise, a period in time when the amount of oscillator drift is measured for producing the drift compensation signal.

11. The method of claim 9 , further comprising:
obtaining, at the PLL device, a first reference clock signal from the master clock reference;
obtaining, at an error detector, a second reference clock signal from the master clock reference; and
generating, at the error detector, a frequency error signal for the PLL device, wherein the frequency error signal compensates for frequency error in the first extracted clock signal.

12. The method of claim 11 ,
wherein the first reference clock signal is from a global positioning system (GPS) source on the master clock reference, and
wherein the second reference clock signal is from synchronous ethernet (SyncE) implemented by the master clock reference over the network.

13. The method of claim 9 ,
wherein the amount of the oscillator drift corresponds to a shifting of an operating frequency of the local oscillator device resulting from temperature effects to the local oscillator device.

14. The method of claim 9 ,
wherein the local oscillator device is an oven-controlled crystal oscillator (OCXO).

Assignees

• Rivaud Daniel
• Estabrooks Kevin
• Abdullah Bashar
• Ciena Corp

Inventors

• Rivaud Daniel
• Estabrooks Kevin
• Abdullah Bashar

Classifications

• H04M2250/10

  including a GPS signal receiver · CPC title

• H04L41/06

  Management of faults, events, alarms or notifications · CPC title

• H04L1/0082

  fields explicitly indicating existence of error in data being transmitted, e.g. so that downstream stations can avoid decoding erroneous packet; relays · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L29/02

  Electricity · mapped topic