Probabilistic digital delay measurement device

Patent metadata

Field	Value
Publication number	US-9843437-B2
Application number	US-201514728034-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 4, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

First claim

The invention claimed is:

1. A method for providing a delay value of a communication electronic unit, the method comprising:
sampling a digital input signal and its corresponding delayed output signal of the communication electronic unit at a sampling interval of a pre-determined length,
comparing an amplitude of the sampled input signal with an amplitude of the sampled output signal,
incrementing a mismatch counting value M each time when the amplitude of the sampled input signal is not equal to the amplitude of the sampled output signal,
incrementing a signal transition counting value N each time the input signal transitions, and
generating the signal delay value between the input signal and the output signal as a probabilistic delay value that is directly proportional to the mismatch counting value M, directly proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value N.

2. The method of claim 1 , wherein the step of sampling comprises simultaneously sampling an input and an output of a delay chain.

3. The method of claim 1 , wherein the sampling is performed by one or more one-bit samplers.

4. The method of claim 1 , wherein the sampling is triggered regularly using a reference clock, wherein a sampling period of the reference clock is different from a clock period of the digital input signal.

5. The method of claim 4 , wherein a multiple of a sampling period of the reference clock that is closest to one clock period of the input signal is offset against a clock period of the input signal by no more than 10% of the clock period of the input signal.

6. The method of claim 1 , wherein transitions of the input signal are derived from the input signal.

7. The method of claim 1 , wherein transitions of the input signal are derived from the output signal.

8. The method of claim 1 , wherein the probabilistic delay value is determined from a time period equal to a time between the transition and an inversion of input and output values.

9. The method of claim 1 , wherein the probabilistic delay value D is calculated using the following equation: D=T_ref*M/N, wherein T_ref is a sampling period between two consecutive sampling times, M is the mismatch counting value and N is the transition counting value.

10. The method of claim 1 , wherein an integration interval after which the delay value is calculated depends on a pre-determined number of input signal transitions.

11. The method of claim 1 , wherein an integration interval after which the delay value is calculated depends on a pre-determined number of mismatches.

12. The method of claim 1 , wherein an integration interval does not exceed a pre-determined integration time.

13. The method of claim 1 , wherein the probabilistic delay value is calculated based on the signal mismatches and transitions that occur within a sliding time window.

14. The method of claim 1 , comprising adjusting of a delay according to the probabilistic delay value, the adjustment comprising deactivating or activating components of a delay chain, the number of components depending on the delay.

15. A delay generator for providing a pre-determined delay of a digital signal input signal, the delay generator comprising
an adjustable delay element with a signal input for receiving an input signal and a signal output for outputting a delayed output signal,
a reference clock,
a signal comparing circuit for comparing the input signal with the output signal at pre-determined sampling times and for counting a number of mismatches between the input signal and the output signal, the pre-determined sampling times of the signal comparing circuit being provided by the reference clock,
a transition detecting circuit which is provided in a signal path of the input signal, the transition detecting circuit being operative to detect signal transitions and to count a number of the signal transitions,
a delay estimation circuit for receiving the number of mismatches from the signal comparing circuit, for receiving the number of signal transitions from the transition detecting circuit and for computing an estimated delay that is proportional to the number of mismatches and inversely proportional to the number of transitions,
a controller that is connected to the delay estimation circuit and to the adjustable delay element for providing a control signal to the adjustable delay element, the control signal depending on the estimated delay.

16. The delay generator according to claim 15 , wherein the controller of the adjustable delay element is operative to adjust the delay by activating and by deactivating individual electronic components of the adjustable delay element.

17. The delay generator according to claim 15 , wherein the signal comparing circuit comprises a first one-bit sampler and a second one-bit sampler.

18. The delay generator according to claim 15 , wherein the signal comparing circuit comprises an XOR gate.

19. An integrated circuit with a delay generator, the delay generator comprising:
an adjustable delay element with a signal input for receiving an input signal and a signal output for outputting a delayed output signal,
a reference clock,
a signal comparing circuit for comparing the input signal with the output signal at pre-determined sampling times and for counting a number of mismatches between the input signal and the output signal, the pre-determined sampling times of the signal comparing circuit being provided by the reference clock,
a transition detecting circuit which is provided in a signal path of the input signal, the transition detecting circuit being operative to detect signal transitions and to count a number of the signal transitions,
a delay estimation circuit for receiving the number of mismatches from the signal comparing circuit, for receiving the number of signal transitions from the transition detecting circuit and for computing an estimated delay that is proportional to the number of mismatches and inversely proportional to the number of transitions,
a controller that is connected to the delay estimation circuit and to the adjustable delay element for providing a control signal to the adjustable delay element, the control signal depending on the estimated delay, the delay generator comprising semiconductor components of the integrated circuit.

20. A communication electronic system, the communication electronic system comprising an integrated circuit with a delay generator, the delay generator comprising:
an adjustable delay element with a signal input for receiving an input signal and a signal output for outputting a delayed output signal,
a reference clock,
a signal comparing circuit for comparing the input signal with the output signal at pre-determined sampling times and for counting a number of mismatches between the input signal and the output signal, the pre-determined sampling times of the signal comparing circuit being provided by the reference clock,
a transition detecting circuit which is provided in a signal path of the input signal, the transition detecting circuit being operative to detect signal transitions and to count a number of the signal transitions,
a delay estimation circuit for receiving the number of mismatches from the signal comparing circuit, for receiving the number of signal transitions from the transition detecting circuit and for computing an estimated delay that is proportional to the number of mismatches and inversely proportional to the number of transitions,
a controller

Assignees

• Lantiq Beteiligungs Gmbh & Co Kg

Inventors

• Povazanec Juraj
• Sukumaran Biju
• Traeber Mario

Classifications

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/06

  by the use of delay lines or other analogue delay elements · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H04L7/0041 Primary

  Delay of data signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title