Multi-modulus frequency divider

Patent metadata

Field	Value
Publication number	US-9843329-B2
Application number	US-201414288166-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	May 27, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider.

First claim

What is claimed is:

1. A frequency divider comprising:
a master frequency divider comprising:
clocking transistor devices to receive a differential input signal having a first frequency at an input of the frequency divider;
memory transistor circuits coupled to the clocking transistor devices to store signals based on the differential input signal from the clocking transistor devices;
write transistor devices coupled to memory transistor circuits to make a divided frequency signal available at a plurality of output terminals of the master frequency divider; and
a current source bias coupled to the clocking transistor devices, wherein the current source bias is configured to apply a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider; and

a slave frequency divider comprising:
slave clocking transistor devices to receive the differential input signal;
slave memory transistor circuits coupled to the slave clocking transistor devices;
slave write transistor devices coupled to the slave memory transistor circuits to make a secondary divided frequency signal available at a plurality of slave output terminals of the slave frequency divider;
control switches for controlling an operation of the slave write transistor devices by controlling when each write cycle of the slave frequency divider outputs from the slave frequency divider depending on the status of the outputs from the master frequency divider, wherein each control switch is coupled to one of the output terminals of the master frequency divider; and
a slave current source bias coupled to the slave clocking transistor devices, wherein the slave current source bias is configured to apply a slave bias current.

2. The frequency divider of claim 1 , wherein the clocking transistor devices, the memory transistor circuits, and the write transistor devices of the master frequency divider are arranged to form a Razavi divider.

3. The frequency divider of claim 1 , wherein the master frequency divider is further configured to operate with the differential input signal having a peak-to-peak amplitude that is less than a rail-to-rail amplitude.

4. The frequency divider of claim 1 , wherein a direct current (DC) level of the clocking transistor devices of the master frequency divider is kept lower than a dropout of the current source bias.

5. The frequency divider of claim 1 , wherein a gate of each clocking transistor device of the master frequency divider is kept higher than a limit for the clocking transistor devices to enter a linear region of operation.

6. The frequency divider of claim 1 , wherein the divided frequency signal available at the output terminals has a frequency equal to the differential input signal divided by two.

7. The frequency divider of claim 1 , wherein the slave frequency divider further comprises mode switches coupled to the slave write transistor devices to control a multimode operation of the frequency divider, wherein each mode of the multimode operation has a unique division factor relative to the differential input signal, and wherein:
in a first mode, the secondary divided frequency signal available at the slave output terminals has a frequency equal to the differential input signal divided by two;
in a second mode, the secondary divided frequency signal available at the slave output terminals has a frequency equal to the differential input signal divided by four; and
in a third mode, the secondary divided frequency signal available at the slave output terminals has a frequency equal to the differential input signal divided by six.

8. The frequency divider of claim 7 , further comprising a controller coupled to the current source bias, wherein the controller is configured to operate the current source bias according to one of a plurality of programmed biasing states corresponding to each mode of the multimode operation.

9. The frequency divider of claim 1 , wherein:
each pair of the slave write switches is coupled together to a single output terminal of the master frequency divider; and
the secondary divided frequency signal available at the slave output terminals has a frequency equal to the differential input signal divided by four.

10. The frequency divider of claim 1 , wherein:
each of the slave write switches is individually coupled to a single output terminal of the master frequency divider; and
the secondary divided frequency signal available at the slave output terminals has a frequency equal to the differential input signal divided by six.

11. A multiband communication circuit comprising:
a high frequency voltage-controlled oscillator (VCO) to output a high frequency clock signal;
a multimode frequency divider coupled to an output of the high frequency VCO, wherein the multimode frequency divider comprises;
a master frequency divider comprising:
clocking transistor devices to receive a differential input signal having a first frequency at an input of the multimode frequency divider;
memory transistor circuits coupled to the clocking transistor devices to store signals based on the differential input signal from the clocking transistor devices;
write transistor devices coupled to memory transistor circuits to make a divided frequency signal available at a plurality of output terminals of the master frequency divider; and
a current source bias coupled to the clocking transistor devices, wherein the current source bias is configured to apply a bias current to adapt the frequency divider to a common-mode at the input of the multimode frequency divider; and

a slave frequency divider comprising:
slave clocking transistor devices to receive the differential input signal;
slave memory transistor circuits coupled to the slave clocking transistor devices;
slave write transistor devices coupled to the slave memory transistor circuits to make a secondary divided frequency signal available at a plurality of slave output terminals of the slave frequency divider;
control switches for controlling an operation of the slave write transistor devices by controlling when each write cycle of the slave frequency divider outputs from the slave frequency divider depending on the status of the outputs from the master frequency divider, wherein each control switch is coupled to one of the output terminals of the master frequency divider; and
a slave current source bias coupled to the slave clocking transistor devices, wherein the slave current source bias is configured to apply a slave bias current; and

a multiband transceiver coupled to an output of the multi mode frequency divider.

12. The multiband communication circuit of claim 11 , wherein the multimode frequency divider is coupled directly to output of the high frequency VCO.

13. The multiband communication circuit of claim 11 , wherein the multiband communication circuit is configured to operate in an absence of a buffer at the output of the high frequency VCO.

14. The multiband communication circuit of claim 11 , wherein the multimode frequency divider is configured to automatically adapt to a common-mode at an input of the multimode frequency divider for compatibility with the high frequency VCO.

15. A method comprising:
receiving a differential input signal at a multimode frequency divider, wherein the multimode frequency divider comprises:
a master frequency divider comprising:
clocking transistor devices to receive a differential input signal having a first frequency at an input of the frequency divider;
memory transistor circuits coupled to the clocking transistor devices to store signals based on the diffe

Assignees

• Nxp Bv

Inventors

• Torres Javier Mauricio Velandia

Classifications

• H03K21/08

  Output circuits · CPC title

• H03K21/02 Primary

  Input circuits · CPC title

• H03B5/12

  active element in amplifier being semiconductor device (H03B5/14 takes precedence) · CPC title

• H04B1/40

  Circuits · CPC title