High-speed low-power latches

Patent metadata

Field	Value
Publication number	US-8970272-B2
Application number	US-12149308-A
Country	US
Kind code	B2
Filing date	May 15, 2008
Priority date	May 15, 2008
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.

First claim

What is claimed is:

1. An apparatus comprising:
a non-inverted clock input;
an inverted clock input;
a non-inverted data signal input;
an inverted data signal input;
a non-inverted output;
an inverted output;
a first set of transistors comprising a first pull-up transistor and a first pull-down transistor configured to receive the inverted clock input and the non-inverted clock input, respectively;
a second set of transistors coupled to the first set of transistors and configured to receive the non-inverted data signal input and the inverted data signal input and provide an inverted output signal at the inverted output and a non-inverted output signal at the non-inverted output, respectively, and wherein the second set of transistors comprises a first transistor having a first transistor drain directly coupled to a first drain of the first set of transistors and to the inverted output; and
a third set of transistors coupled to the second set of transistors and configured to form a latch.

2. The apparatus of claim 1 , wherein:
the first pull-up transistor is a PMOS transistor comprising a first pull-up transistor source, a first pull-up transistor gate and a first pull-up transistor drain;
the first pull-up transistor is configured to couple the first pull-up transistor source to a V DD supply, the first pull-up transistor gate to the inverted clock input, and the first pull-up transistor drain to the second set of transistors;
the first pull-down transistor is an NMOS transistor having a first pull-down transistor source, a first pull-down transistor gate and a first pull-down transistor drain; and
the first pull-down transistor is configured to couple the first pull-down transistor source to ground, the first pull-down transistor gate to the non-inverted clock input, and the first pull-down transistor drain to the second set of transistors.

3. The apparatus of claim 2 , wherein the first set of transistors comprises a second pull-up transistor, wherein:
the second pull-up transistor is a PMOS transistor comprising a second pull-up transistor source, a second pull-up transistor gate and a second pull-up transistor drain; and
the second pull-up transistor is configured to couple the second pull-up transistor source to the V DD supply, the second pull-up transistor gate to the inverted clock input, and the second pull-up transistor drain to the second set of transistors.

4. The apparatus of claim 2 , wherein the first set of transistors comprises a second pull-down transistor, wherein:
the second pull-down transistor is an NMOS transistor comprising a second pull-down transistor source, a second pull-down transistor gate and a second pull-down transistor drain; and
the second pull-down transistor is configured to couple the second pull-down transistor source to ground, the second pull-down transistor gate to the non-inverted clock input, and the second pull-down transistor drain to the second set of transistors.

5. The apparatus of claim 2 , wherein the second set of transistors further comprises:
the first transistor, the first transistor having a first transistor source, and a first transistor gate, wherein the first transistor is configured to couple the first transistor gate to the non-inverted data signal input and the first transistor source to a second drain of the first set of transistors; and
a second transistor, the second transistor having a second transistor source, a second transistor gate and a second transistor drain, wherein the second transistor is configured to couple the second transistor gate to the inverted data signal input, the second transistor source to the second drain of the first set of transistors and the second transistor drain to a third drain of the first set of transistors and to the non-inverted output.

6. The apparatus of claim 5 ,
wherein the first transistor comprises a first PMOS transistor having a first PMOS transistor gate, a first PMOS transistor source, and a first PMOS transistor drain, wherein the first pull-up transistor drain is coupled to the first PMOS transistor source, the first PMOS transistor gate is coupled to the non-inverted data signal input, and the first PMOS transistor drain is coupled to the inverted output; and
wherein the second transistor comprises a second PMOS transistor having a second PMOS transistor gate, a second PMOS transistor source, and a second PMOS transistor drain, wherein the first pull-up transistor drain is coupled to the second PMOS transistor source, the second PMOS transistor gate is coupled to the inverted data signal input, and the second PMOS transistor drain is coupled to the non-inverted output.

7. The apparatus of claim 2 , wherein said latch comprises:
a third NMOS transistor having a third NMOS transistor gate, a third NMOS transistor source, and a third NMOS transistor drain, wherein the third NMOS transistor gate is coupled to the non-inverted output, the third NMOS transistor drain is coupled to the inverted output, and the third NMOS transistor source is coupled to ground, and
a fourth NMOS transistor having a fourth NMOS transistor gate, a fourth NMOS transistor source and a fourth NMOS transistor drain, wherein the fourth NMOS transistor gate is coupled to the inverted output, the fourth NMOS transistor drain is coupled to the non-inverted output, and the fourth NMOS transistor source is coupled to ground.

8. The apparatus of claim 2 , wherein said latch comprises:
a third PMOS transistor having a third PMOS transistor gate, a third PMOS transistor source, and a third PMOS transistor drain, wherein the third PMOS transistor gate is coupled to the non-inverted output, the third PMOS transistor drain is coupled to the inverted output, and the third PMOS transistor source is coupled to the VDD supply, and
a fourth PMOS transistor having a fourth PMOS transistor gate, a fourth PMOS transistor source and a fourth PMOS transistor drain, wherein the fourth PMOS transistor gate is coupled to the inverted output, the fourth PMOS transistor drain is coupled to the non-inverted output, and the fourth PMOS transistor source is coupled to the V DD supply.

9. The apparatus of claim 2 , wherein said latch comprises a first inverter and a second inverter cross-coupled with one another such that a first inverter output is coupled to a second inverter input and provides an inverted output signal at the inverted output and such that a second inverter output is coupled to a first inverter input and provides an non-inverted output signal at the non-inverted output.

10. The apparatus of claim 1 , wherein the transistors in the first set have stronger drive strength, when enabled, than the transistors in the third set.

11. The apparatus of claim 1 , wherein the third set of transistors is configured to provide amplification during a tracking mode.

12. An integrated circuit comprising:
a non-inverted clock input;
an inverted clock input;
a non-inverted data signal input;
an inverted data signal input;
a non-inverted output;
an inverted output;
a first set of transistors comprising a first pull-up transistor and a first pull-down transistor configured to receive the inverted clock input and the non-inverted clock input, respectively;
a second set of transistors coupled to the first set of transistors and configured to receive the non-inverted data signal input and the inverted data signal input and provide an inverted output signal at the inverted output and a non-inverted output signal at the non-inverted output, respectively, and wherein the second set of transistors comprises a first transistor having a first transistor drain directly coupled to a first drain o

Assignees

• Zhang Kun
• Muthali Harish
• Qualcomm Inc

Inventors

• Zhang Kun
• Muthali Harish

Classifications

• H03K3/356139 Primary

  with synchronous operation · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title