Vertical type semiconductor devices and methods of manufacturing the same
US-2024172441-A1 · May 23, 2024 · US
Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
US9136376B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136376-B2 |
| Application number | US-201313759395-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 5, 2013 |
| Priority date | Mar 12, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a plurality of active pillars, each of the active pillars including a first impurity region disposed over a surface of a substrate, a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is arranged at a constant interval over the first impu…
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Electricity · mapped topic
- H10D30/025Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136376B2 cover?
- A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes a…
- Who is the assignee on this patent?
- Sk Hynix Inc, Korea Advanced Inst Sci & Tech
- What technology area does this patent fall under?
- Primary CPC classification H10D30/025. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).