Power semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-8963260-B2
Application number	US-201313902850-A
Country	US
Kind code	B2
Filing date	May 26, 2013
Priority date	Mar 26, 2013
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.

First claim

What is claimed is:

1. A power semiconductor device, comprising:
a cell region on a semiconductor substrate;
at least one transistor device disposed in the cell region;
a peripheral termination region surrounding the cell region;
a transition region interposed between the cell region and the peripheral termination region;
a guard ring doping region in the transition region;
a gate structure disposed on the guard ring doping region;
a plurality of islands of first epitaxial layer disposed in the peripheral termination region; and
a grid-shaped second epitaxial layer in the peripheral termination region, the grid-shaped second epitaxial layer surrounds each of the plurality of islands of first epitaxial layer to thereby separate the plurality of islands of first epitaxial layer from one another.

2. The power semiconductor device according to claim 1 wherein the plurality of islands of first epitaxial layer have a first conductivity type, the semiconductor substrate has a second conductivity type, the grid-shaped second epitaxial layer has the second conductivity type.

3. The power semiconductor device according to claim 2 wherein the first conductivity type is P type and the second conductivity is N type.

4. The power semiconductor device according to claim 2 further comprising a third epitaxial layer between the first epitaxial layer, the second epitaxial layer and the semiconductor substrate.

5. The power semiconductor device according to claim 4 wherein the third epitaxial layer has the second conductivity type.

6. The power semiconductor device according to claim 1 wherein the transistor device comprises at least one straight line-shaped said first epitaxial layer and at least one straight line-shaped said second epitaxial layer, an ion well at an upper portion of the first epitaxial layer, and a source doping region in the ion well.

7. The power semiconductor device according to claim 1 further comprising at least one continuous, annular doping region in the peripheral termination region to string the plurality of islands of first epitaxial layer.

8. The power semiconductor device according to claim 7 wherein the continuous, annular doping region has the first conductivity type.

9. The power semiconductor device according to claim 1 wherein the transition region has an annular shape.

10. The power semiconductor device according to claim 1 wherein the guard ring doping region has the first conductivity type.

11. The power semiconductor device according to claim 1 wherein the gate structure traverses the transition region and the peripheral termination region and extends to a field oxide layer.

12. The power semiconductor device according to claim 1 wherein the gate structure is composed of polysilicon.

Assignees

• Anpec Electronics Corp

Inventors

• Lin Yung-Fa
• Chang Chia-Hao

Classifications

• H10D64/111 Primary

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title