Electronic component package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9842789-B2
Application number	US-201615140775-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	May 11, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

First claim

What is claimed is:

1. An electronic component package comprising:
a frame having a cavity;
an electronic component disposed in the cavity of the frame;
a first metal layer disposed on an inner wall of the cavity of the frame;
a second metal layer disposed on a lower surface of the frame;
a third metal layer disposed on an upper surface of the frame;
a penetration wiring penetrating through the frame;
an encapsulant encapsulating at least portion of the electronic component; and
a redistribution layer disposed below the frame and the electronic component, wherein the second and third metal layers are redistribution patterns or dummy patterns.

2. The electronic component package of claim 1 , wherein the first metal layer encloses around side surfaces of the electronic component.

3. The electronic component package of claim 2 , wherein the first metal layer entirely covers the inner wall of the cavity of the frame.

4. The electronic component package of claim 1 , wherein the second metal layer is connected to the first metal layer.

5. The electronic component package of claim 1 , wherein the second metal layer entirely covers the lower surface of the frame.

6. The electronic component package of claim 1 , wherein the third metal layer is connected to the first metal layer.

7. The electronic component package of claim 1 , wherein the third metal layer entirely covers the upper surface of the frame.

8. The electronic component package of claim 1 , further comprising:
an external layer disposed below the redistribution layer and having an opening; and
an external connection terminal disposed in the opening,
wherein at least one external connection terminal is disposed in a fan-out region.

9. The electronic component package of claim 1 , wherein the encapsulant fills a space in the cavity of the frame while covering upper portions of the frame and the electronic component.

10. The electronic component package of claim 9 , wherein the encapsulant encloses outer side surfaces of the frame, and the frame is not externally exposed.

11. A method of manufacturing an electronic component package, the method comprising:
preparing a frame having a cavity;
forming a first metal layer on an inner wall of the cavity of the frame;
forming a second metal layer on a lower surface of the frame;
forming a third metal layer on an upper surface of the frame;
forming a penetration wiring penetrating through the frame;
disposing an electronic component in the cavity of the frame;
forming an encapsulant encapsulating at least portion of the electronic component; and
forming a redistribution layer below the frame and the electronic component, wherein the second and third metal layers are redistribution patterns or dummy patterns.

12. The method of claim 11 ,
wherein the first to third metal layers are simultaneously formed.

Assignees

• Samsung Electro Mech

Inventors

• Kang Seung On
• Han Woo Sung
• Ko Young Gwan
• Kim Chul Kyu
• Kim Han

Classifications

• H10W42/284

  shielding resins · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/473

  containing a filler · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title