Semiconductor device and method of forming a thin wafer without a carrier

Patent metadata

Field	Value
Publication number	US-9842775-B2
Application number	US-201615218536-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Mar 26, 2009
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a conductive via partially through the semiconductor die and exposed at a first surface of the semiconductor die;
forming a first redistribution layer over the first surface of the semiconductor die and coupled to the conductive via;
forming a first solder bump over the first redistribution layer, wherein the first solder bump is electrically coupled to the conductive via through the first redistribution layer;
depositing an encapsulant over the first surface of the semiconductor die to completely cover the first redistribution layer and first solder bump;
removing a portion of the semiconductor die opposite the first surface after depositing the encapsulant to expose the conductive via and create a second surface of the semiconductor die;
forming a second redistribution layer over the second surface of the semiconductor die and coupled to the conductive via; and
forming a second solder bump over the second redistribution layer, wherein the second solder bump is electrically coupled to the conductive via through the second redistribution layer.

2. The method of claim 1 , further including forming the second solder bump laterally offset from the conductive via.

3. The method of claim 1 , further including forming the first solder bump laterally offset from the conductive via.

4. The method of claim 1 , further including forming a third solder bump directly on the first solder bump over the encapsulant.

5. A method of making a semiconductor device, comprising:
providing a substrate;
forming a conductive via partially through the substrate;
forming a first redistribution layer over a first surface of the substrate;
forming a first bump over the first surface of the substrate with the first redistribution layer between the conductive via and first bump;
depositing an encapsulant over the first surface of the substrate covering the first bump and first redistribution layer;
removing a portion of the substrate opposite the encapsulant to expose the conductive via;
forming a second redistribution layer over a second surface of the substrate after removing the portion of the substrate; and
forming a second bump over the second surface of the substrate with the second redistribution layer between the conductive via and second bump.

6. The method of claim 5 , further including forming the second bump laterally offset from the conductive via.

7. The method of claim 5 , further including forming the first bump laterally offset from the conductive via.

8. The method of claim 5 , further including forming a third bump over the first bump and encapsulant.

9. The method of claim 5 , further including forming an interconnect structure over the first surface of the substrate prior to forming the first bump.

10. The method of claim 5 , wherein the substrate includes a semiconductor die.

11. A method of making a semiconductor device, comprising:
providing a substrate;
forming a conductive via partially through the substrate;
forming a first interconnect structure over a first surface of the substrate;
depositing an encapsulant over the first surface of the substrate to cover the first interconnect structure;
removing a portion of the substrate to expose the conductive via after depositing the encapsulant; and
forming a second interconnect structure over a second surface of the substrate opposite the first surface of the substrate.

12. The method of claim 11 , wherein the first interconnect structure includes a solder bump.

13. The method of claim 11 , wherein the second interconnect structure includes a solder bump.

14. The method of claim 11 , further including forming the first interconnect structure laterally offset from the conductive via.

15. The method of claim 11 , further including forming the second interconnect structure laterally offset from the conductive via.

16. The method of claim 11 , wherein the substrate includes a semiconductor die.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Marimuthu Pandi C
• Huang Shuangwu
• Suthiwongsunthorn Nathapong

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/50

  Bond wires · CPC title