Reflow enhancement layer for metallization structures

Patent metadata

Field	Value
Publication number	US-9842770-B1
Application number	US-201615189749-A
Country	US
Kind code	B1
Filing date	Jun 22, 2016
Priority date	Jun 22, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a reflow enhancement liner located in at least a portion of an opening present in a dielectric-containing substrate, said reflow enhancement liner having a horizontal portion and two vertical portions extending from opposite ends of said horizontal portion; and
a metallization structure located on said horizontal portion of said reflow enhancement liner and completely filling a volume located between said two vertical portions of said reflow enhancement liner, wherein said reflow enhancement liner and said metallization structure have topmost surfaces that are coplanar with each other and are located entirely within said opening, and wherein said reflow enhancement liner is of a different composition than said metallization structure.

2. The semiconductor structure of claim 1 , wherein said metallization structure comprises cobalt.

3. The semiconductor structure of claim 2 , wherein said reflow enhancement liner is composed of a metal or metal alloy selected from the group consisting of ruthenium, iridium, a tantalum-iridium alloy, a niobium-ruthenium alloy and a niobium-iridium alloy.

4. The semiconductor structure of claim 1 , further comprising a diffusion barrier liner located beneath, and in direct with, said reflow enhancement liner.

5. The semiconductor structure of claim 4 , wherein dielectric-containing structure is entirely composed of a middle-of-the line dielectric material layer.

6. The semiconductor structure of claim 5 , wherein said topmost surfaces of each of said reflow enhancement liner and said metallization structure are coplanar with a topmost surface of said middle-of-the-line dielectric material layer.

7. The semiconductor structure of claim 6 , further comprising a cap located on said topmost surfaces of said reflow enhancement liner, said metallization structure and said middle-of-the-line dielectric material layer.

8. The semiconductor structure of claim 1 , further comprising a gate dielectric portion and a work function metal portion located beneath said reflow enhancement liner, wherein said work function metal portion directly contacts said reflow enhancement liner.

9. The semiconductor structure of claim 8 , wherein said dielectric-containing substrate includes a pair of dielectric spacers surrounding said opening, and wherein said reflow enhancement liner and said metallization structure are located in a bottom portion of said opening.

10. The semiconductor structure of claim 9 , further comprising a cap located in an upper portion of said opening.

11. The semiconductor structure of claim 10 , wherein said cap is located on said topmost surfaces of each of said reflow enhancement liner and said metallization structure, and wherein said cap has a topmost surface that is coplanar with a topmost surface of said middle-of-the-line dielectric material layer.

12. A semiconductor structure comprising:
a reflow enhancement liner located in an opening present in a middle-of-the-line dielectric material layer that is located on a surface of a semiconductor substrate containing at least one semiconductor device, said reflow enhancement liner having a horizontal portion and two vertical portions extending from opposite ends of said horizontal portion; and
a metallization structure located on said horizontal portion of said reflow enhancement liner and completely filling a volume located between said two vertical portions of said reflow enhancement liner, wherein said metallization structure, said reflow enhancement liner, and said middle-of-the-line dielectric material layer have topmost surfaces that are coplanar with each other, and said reflow enhancement liner and said metallization structure are located entirely within said opening present in said middle-of-the-line dielectric material, and wherein said reflow enhancement liner is of a different composition than said metallization structure.

13. A semiconductor structure comprising:
a gate cavity present in a middle-of-the-line dielectric material layer that is located above a semiconductor fin;
a dielectric spacer located in said at least one gate cavity, said dielectric spacer having a topmost surface that is coplanar with a topmost structure of said middle-of-the-line dielectric material layer;
a gate dielectric portion located adjacent each dielectric spacer and in a lower portion of said at least one gate cavity;
a work function metal portion located on said gate dielectric portion and in said lower portion of said at least one gate cavity;
a reflow enhancement liner located on said work function metal portion and in said lower portion of said at least one gate cavity, said reflow enhancement liner having a horizontal portion and two vertical portions extending from opposite ends of said horizontal portion therein; and
a metallization structure located on said horizontal portion of said reflow enhancement liner and completely filling a volume located between said two vertical portions of said reflow enhancement liner, wherein a topmost surface of said gate dielectric portion, said work function metal portion, said reflow enhancement liner, and said metallization structure are coplanar with each other and are vertically offset and located beneath said topmost surface of said middle-of-the-line dielectric material layer, and wherein said reflow enhancement liner is of a different composition than said metallization structure.

Assignees

• IBM

Inventors

• Adusumilli Praneet
• Reznicek Alexander
• Van Der Straten Oscar

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title