Three-dimensional vertical NOR flash thin film transistor strings

Patent metadata

Field	Value
Publication number	US-9842651-B2
Application number	US-201615343332-A
Country	US
Kind code	B2
Filing date	Nov 4, 2016
Priority date	Nov 25, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

First claim

I claim:

1. A memory structure, comprising:
a semiconductor substrate having a substantially planar surface and including circuitry formed therein for supporting a memory circuit;
a plurality of active columns of semiconducting material formed above the semiconductor substrate, each active column extending along a first direction orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped regions, wherein the active columns are arranged in a two-dimensional array having rows of active columns extending along a second direction and rows of active columns extending along a third direction, the second direction and the third direction each being parallel to the planar surface of the semiconductor substrate;
charge-trapping material provided over one or more surfaces of each active columns; and
a plurality of conductors provided between the active columns in a plurality of stacks, each stack extending lengthwise along the third direction, wherein the active columns, the charge-trapping material and the conductors together form a plurality of variable-threshold thin film transistors, each variable-threshold thin film transistor comprising an associated one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions.

2. The memory structure of claim 1 , wherein (i) the first heavily doped region forms a bit line and serves as a first drain or source terminal of the variable-threshold thin film transistor, the bit line connecting the first drain or source terminal to the circuitry in the semiconductor substrate, (ii) the associated conductor provides a word line and serves as a gate terminal to provide a control voltage to the variable-threshold thin film transistor, during a read operation; and (iii) the second heavily doped region forms a source line and serves as a second drain or source terminal of the variable-threshold thin film transistor, the source line having a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

3. The memory structure of claim 2 , further comprising a pre-charge transistor for charging the capacitance to a predetermined voltage prior to the read operation.

4. The memory structure of claim 2 wherein, during the read operation, the control voltage causes the non-volatile storage transistor to discharge the capacitance, when the sum of the control voltage and the predetermined voltage difference exceeds the variable threshold voltage.

5. The memory structure of claim 1 , wherein the semiconductor material comprises polysilicon.

6. The memory structure of claim 1 , wherein the active columns are isolated from each other by an isolation dielectric material or by an air gap.

7. The memory structure of claim 1 , wherein the plurality of conductors in a stack are insulated from each other by an isolation dielectric material or air gap.

8. The memory structure of claim 1 , wherein the conductor adjacent each variable-threshold thin film transistor serves as a control gate for the variable-threshold thin film transistor.

9. The memory structure of claim 1 , wherein the variable-threshold thin film transistors associated with each active column are organized in parallel into one or more NOR thin film transistor strings.

10. The memory structure of claim 9 , wherein the first and second heavily doped regions of each active column serve as a common local source line and a common local drain or bit line, respectively, for the variable-threshold thin film transistors associated with the corresponding active column, and the lightly doped region serves as individual channels of the variable-threshold thin film transistors comprising the NOR string.

11. The memory structure of claim 10 , wherein the local source line electrically floats when all the variable-threshold thin film transistors are non-conducting and wherein the local source line has a parasitic capacitance that provides a virtual voltage source for the variable-threshold thin film transistors of the active column.

12. The memory structure of claim 11 , wherein the parasitic capacitance is further enhanced by providing additional one or more dummy word lines capacitively coupled to the local source line.

13. The memory structure of claim 11 , wherein one or more variable-threshold thin film transistors of the active column serve as dedicated pre-charge transistors for charging the parasitic capacitance to a predetermined voltage.

14. The memory structure of claim 11 , wherein the circuitry for supporting a memory circuit comprises a voltage drop detector selectably connected to one of the variable-threshold thin film transistors to detect a voltage drop resulting from the variable-threshold thin film transistor being rendered conducting during a read operation.

15. The memory structure of claim 11 , wherein the conductors are located on a plurality of planes that are each substantially parallel to the planar surface of the semiconductor substrate, and wherein, during programming, the local bit line of each active column is selectively charged to a programming voltage or a program-inhibit voltage, after which programming gate voltages are applied to conductors of a selected plane, while conductors not in the selected planes are held to a non-programming gate voltage.

16. The memory structure of claim 15 wherein, during programming, the local bit line of each active column is selectively charged to one of several programming voltages representative of several threshold voltages of a multistate thin film transistor or to a program-inhibit voltage, after which programming gate voltages are applied to conductors of a selected plane to program in parallel the several threshold voltages and inhibit further programming of those thin film transistors that are read to have reached their predetermined threshold voltage.

17. The memory structure of claim 11 , wherein programming or reading of the variable-threshold thin film transistors proceeds in parallel on multiple active columns, after pre-charging local source lines of the active columns to set the virtual voltage source to predetermined voltages.

18. The memory structure of claim 17 wherein, during the programming or reading of the variable-threshold thin film transistors, the virtual voltage sources provide currents in the conducting variable-threshold thin film transistors, thereby avoiding drawing the currents simultaneously form a common voltage source.

19. The memory structure of claim 10 , further comprising global source lines, each global source line comprising a conductor extending along the second direction, the global source lines selectively interconnecting the common local source line of each active column to the supply circuitry in the semiconductor substrate.

20. The memory structure of claim 19 , wherein the global source lines are provided between the planar surface of the semiconductor substrate and the array of active columns.

21. The memory structure of claim 19 , wherein charge is stored into the charge-trapping material using channel hot-electron injection programming approach.

22. The memory structure of claim 21 , wher

Assignees

• Harari Eli
• Sunrise Memory Corp

Inventors

• Harari Eli

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title