Programming of resistive random access memory for analog computation

Patent metadata

Field	Value
Publication number	US-9842647-B1
Application number	US-201615267124-A
Country	US
Kind code	B1
Filing date	Sep 15, 2016
Priority date	Sep 15, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Examples include a method of programming resistive random access memory (RRAM) array for analog computations. In some examples, a selected RRAM cell of the RRAM array may be programmed with a selected target conductance and a programmed conductance error of the selected RRAM cell may be determined. A neighboring RRAM cell may be programmed with an error corrected target conductance that is a function of a neighboring target conductance and the programmed conductance error of the selected RRAM cell. The neighboring RRAM cell may be in a same row or a same column as the selected RRAM cell. The selected RRAM cell and neighboring RRAM cell are programmed such that the RRAM array is programmed for an analog computation.

First claim

What is claimed is:

1. A method of programming a resistive random access memory (RRAM) array for an analog computation, the method comprising:
programming a selected RRAM cell of the RRAM array with a selected target conductance;
determining a programmed conductance error of the selected RRAM cell; and
programming a neighboring RRAM cell with an error corrected target conductance,
wherein the neighboring RRAM cell is in a same row as the selected RRAM cell or a same column as the selected RRAM cell,
wherein the error corrected target conductance is a function of a neighboring target conductance and the programmed conductance error of the selected RRAM cell; and
wherein the selected RRAM cell and the neighboring RRAM cell are programmed such that the RRAM array is programmed for the analog computation.

2. The method of claim 1 , wherein the selected RRAM cell of the RRAM array is an nth RRAM cell, where n is a nearest integer of N/2, and where N is a number of cells in a column or a row of the RRAM array and is a positive integer greater than one.

3. The method of claim 1 , wherein programming the neighboring RRAM cell further comprises:
programming a first neighboring RRAM cell with a first error corrected target conductance, wherein the first error corrected target conductance is a function of a first target conductance and the programmed conductance error of the selected RRAM cell; and
programming a second neighboring RRAM cell with a second error corrected target conductance, wherein the second error corrected target conductance is a function of a second target conductance and the programmed conductance error of the selected RRAM cell.

4. The method of claim 3 ,
wherein the first error corrected conductance is the first target conductance of the first neighboring RRAM cell reduced by a first factor of the programmed conductance error of the selected RRAM cell,
wherein the second error corrected conductance is the second target conductance of the second neighboring RRAM cell reduced by a second factor of the programmed conductance error of the selected RRAM cell, and
wherein the first factor and the second factor are each a positive fraction equal to or between 0 and 1.

5. The method of claim 4 , wherein a sum of the first factor and the second factor is equal to 1.

6. The method of claim 5 , wherein the first factor equals the second factor.

7. The method of claim 4 , wherein programming the neighboring RRAM cell further comprises:
programming a third neighboring RRAM cell with a third error corrected target conductance, wherein the third error corrected target conductance is a function of a third target conductance and the programmed conductance error of the selected RRAM cell; and
programming a fourth neighboring RRAM cell with a fourth error corrected target conductance, wherein the fourth error corrected target conductance is a function of a fourth target conductance and the programmed conductance error of the selected RRAM cell.

8. The method of claim 7 ,
wherein the third error corrected conductance is the third target conductance of the third neighboring RRAM cell reduced by a third factor of the programmed conductance error of the selected RRAM cell,
wherein the fourth error corrected conductance is the fourth target conductance of the fourth neighboring RRAM cell reduced by a fourth factor of the programmed conductance error of the selected RRAM cell, and
wherein the third factor and the fourth factor are each a positive fraction equal to or between 0 and 1.

9. The method of claim 8 , wherein the sum of the first factor, the second factor, the third factor, and the fourth factor is equal to 1.

10. The method of claim 4 , wherein programming the neighboring RRAM cell further comprises:
programming a third neighboring RRAM cell with a third error corrected target conductance, wherein the third error corrected target conductance is a function of a third target conductance and a programmed conductance error of the first neighboring RRAM cell; and
programming a fourth neighboring RRAM cell with a fourth error corrected target conductance, wherein the fourth error corrected target conductance is a function of a fourth target conductance and a programmed conductance error of the second RRAM cell.

11. The method of claim 10 ,
wherein the third error corrected conductance is the third target conductance of the third neighboring RRAM cell reduced by a third factor of the programmed conductance error of the first neighboring RRAM cell,
wherein the fourth error corrected conductance is the fourth target conductance of the fourth neighboring RRAM cell reduced by a fourth factor of the programmed conductance error of the second neighboring RRAM cell, and
wherein the third factor and the fourth factor are each a positive fraction equal to or between 0 and 1.

12. A resistive random access memory (RRAM) array programmed for an analog computation comprising:
a selected RRAM cell of the RRAM array that is programmed with a selected target conductance;
a first neighboring RRAM cell that is programmed with a first error corrected target conductance, wherein the first error corrected target conductance is a function of a first target conductance and a programmed conductance error of the selected RRAM cell; and
a second neighboring RRAM cell that is programmed with a second error corrected target conductance,
wherein the second error corrected target conductance is a function of a second target conductance and the programmed conductance error of the selected RRAM cell, and
wherein the selected RRAM cell, the first neighboring RRAM cell, and the second neighboring RRAM cell are programmed such that the RRAM array is programmed for the analog computation.

13. The RRAM array of claim 12 , wherein the first neighboring RRAM cell and the second neighboring cell are adjacent to the selected RRAM cell in a same row as the selected RRAM cell or in a same column as the selected RRAM cell.

14. The RRAM array of claim 12 , wherein the first target conductance and the second target conductance are together reduced by an amount equal to the programmed conductance error of the selected RRAM cell to calculate the first error corrected target conductance and the second error corrected target conductance.

15. The RRAM array of claim 14 , further comprising:
a third neighboring RRAM cell that is programmed with a third error corrected target conductance, wherein the third error corrected target conductance is a function of a third target conductance and a programmed conductance error of the selected RRAM cell; and
a fourth neighboring RRAM cell that is programmed with a fourth error corrected target conductance,
wherein the fourth error corrected target conductance is a function of a fourth target conductance and the programmed conductance error of the selected RRAM cell, and
wherein the third neighboring RRAM cell and the fourth neighboring RRAM cell are programmed such that the RRAM array is programmed for the analog computation.

16. The RRAM array of claim 14 , wherein the first target conductance, the second target conductance, the third target conductance, and the fourth target conductance are together reduced by an amount equal to the programmed conductance error of the selected RRAM cell to calculate the first error corrected conductance, the second error corrected conductance, the third error corrected conductance, and the fourth error corrected conductance.

17. A non-transitory machine-readable storage medium comprising instructions executable by a process

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Strachan John Paul
• Buchanan Brent
• Merced Grafals Emmanuelle

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C27/00

  Electric analogue stores, e.g. for storing instantaneous values · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title