Sensing a non-volatile memory device utilizing selector device holding characteristics

Patent metadata

Field	Value
Publication number	US-2016005461-A1
Application number	US-201514755998-A
Country	US
Kind code	A1
Filing date	Jun 30, 2015
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

First claim

What is claimed is:

1 . A method for sensing data stored in a non-volatile memory in electrical series with a volatile selection device, comprising:
applying a first voltage across a first electrode and a second electrode of the non-volatile memory having a magnitude larger than an activation magnitude of the volatile selection device, thereby switching the volatile selection device from a high selection resistance to a low selection resistance; applying a second voltage across the first electrode and the second electrode having a second magnitude smaller than the activation magnitude of the volatile selection device; and determining a data value stored by the non-volatile memory in response to the non-volatile memory.

2 . The method of claim 1 , wherein applying the first voltage further comprises selecting the first voltage from between about 2 volts and about 2.5 volts.

3 . The method of claim 1 , wherein applying the second voltage further comprises selecting the second voltage from between about 0.5 volts and about 1.5 volts.

4 . The method of claim 1 , wherein determining the data value further comprises measuring a value of a read current through the non-volatile memory in response to the second voltage and determining a resistive state of the non-volatile memory from the value of the read current; and at least one of:
determining the resistive state to be a high memory resistance in response to the read current having a first read current value; or determining the resistive state to be a low memory resistance in response to the read current having a second read current value.

5 . The method of claim 4 , wherein a ratio of the first read current value to the second read current value is within a range of about 10E3 to about 10E4.

6 . The method of claim 4 , wherein:
an on-off read current ratio of an on-state current value for the non-volatile memory in a conductive state, to an off-state current value for the non-volatile memory in a non-conductive state, is between about 10E2 and about 10E3.5 in response to applying the first voltage across the first electrode and the second electrode; and the on-off read current ratio of the on-state current value to the off-state current value is between about 10E4.5 and about 10E9 in response to applying the second voltage across the first electrode and the second electrode.

7 . The method of claim 4 , further comprising applying a precharge voltage across the first electrode and the second electrode having a third magnitude below the activation magnitude.

8 . The method of claim 7 , wherein applying the precharge voltage is implemented prior to applying the first voltage.

9 . The method of claim 7 , wherein applying the precharge voltage causes an initial current through the non-volatile memory, wherein a ratio of a value of the initial current to the value of the read current is within a range of about 10E6 to about 10E9.

10 . The method of claim 7 , further comprising applying the precharge voltage for a duration selected from about 50 nanoseconds (ns) to about 200 ns.

11 . The method of claim 1 , further comprising applying the first voltage for a duration selected from about 50 ns to about 200 ns.

12 . A method of reading a one-transistor, multiple-resistor (1TnR) array of resistive memory, comprising:
applying a disturb inhibition voltage to a non-target bitline of a 1TnR memory cell array; applying a second disturb inhibition voltage to a non-target wordline of the 1TnR memory cell array; applying an activation voltage across a target bitline and a target wordline of the 1TnR resistive memory cell array, the target bitline and target wordline are respectively connected to a target memory cell; applying a hold voltage across the target bitline and the target wordline, the hold voltage having a magnitude less than the activation voltage; and measuring a read current value through the target memory cell in response to applying the hold voltage.

13 . The method of claim 12 , wherein applying the activation voltage further comprises applying a voltage within a range of about 2 volts to about 3 volts.

14 . The method of claim 12 , wherein applying the hold voltage further comprises applying a voltage within a range of about 0.5 volts to about 2 volts.

15 . The method of claim 12 , wherein applying the hold voltage further comprises decreasing the activation voltage from a first range of about 2.2 volts to about 2.6 volts, to a second range of about 0.5 volts to about 1.5 volts.

16 . The method of claim 12 , wherein applying the disturb inhibition voltage or the second disturb inhibition voltage further comprises applying a voltage within a range of about 1 volts to about 2 volts.

17 . The method of claim 12 , further comprising applying a precharge voltage across the target bitline and the target wordline prior to applying the activation voltage.

18 . The method of claim 17 , further comprising maintaining the precharge voltage for a period between about 50 nanoseconds (ns) and about 200 ns.

19 . The method of claim 17 , further comprising maintaining the activation voltage for a period between about 50 ns and about 200 ns.

20 . The method of claim 12 , further comprising employing a sensing margin of 10E6 or greater for measuring the read current value in response to applying the hold voltage.

Assignees

• Crossbar Inc

Inventors

• Jo Sung Hyun
• Nazarian Hagop
• Shih Liu Lin

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C14/0045

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C29/026

  in sense amplifiers · CPC title