Spin transistor memory

Patent metadata

Field	Value
Publication number	US-9842635-B2
Application number	US-201615063808-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Mar 20, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

First claim

The invention claimed is:

1. A spin transistor memory comprising at least one cell string,
the at least one cell string including:
first to n-th (n≧3) semiconductor regions of a first conductivity type disposed in a semiconductor layer;
n−1 gates, of which an i-th (i=1, . . . , n−1) gate is disposed above the semiconductor layer between an i-th semiconductor region and an (i+1)-th semiconductor region; and
n ferromagnetic layers, of which an i-th (i=1, . . . , n) ferromagnetic layer is disposed on the i-th semiconductor region,

wherein when m is at least one of 1, . . . , n−1, a m-th and (m+1)-th ferromagnetic layers having variable magnetization directions exist in the n ferromagnetic layers.

2. The memory according to claim 1 , wherein:
one of the first to the n-th ferromagnetic layer is a k-th (1≦k≦n−1) ferromagnetic layer, directions of magnetization of a (k+1)-th ferromagnetic layer to the n-th ferromagnetic layer are expressed as a bit of 0 or 1, depending on whether the directions of magnetization are parallel to or antiparallel to a direction of magnetization of the k-th ferromagnetic layer, and a group of bits in which the bits are arranged from that of the (k+1)-th ferromagnetic layer to that of the n-th ferromagnetic layer is set as a first code;
resistance values between adjacent ferromagnetic layers from the k-th ferromagnetic layer to the n-th ferromagnetic layer are expressed as a bit of 0 or 1, a group of bits in which the bits are arranged from that of the k-th ferromagnetic layer to the n-th ferromagnetic layer is set as a second code; and
a conversion from the first code to the second code is a conversion from a binary code to a Gray code.

3. The memory according to claim 2 , wherein the one of the first to n-th ferromagnetic layer is the first ferromagnetic layer.

4. The memory according to claim 2 , wherein the first code is an input value inputted to the cell string, and the second code is an output value outputted from the cell string.

5. The memory according to claim 4 , further comprising a converter configured to convert a Gray code to a binary code, the converter being disposed on an output side of the cell string and receiving the output value as an input.

6. The memory according to claim 4 , further comprising a converter configured to convert a Gray code to a binary code, the converter being disposed on an input side of the cell string, and the cell string receiving an output of the converter as the input value.

7. The memory according to claim 1 , further comprising a nonmagnetic layer disposed between the i-th semiconductor region and the i-th ferromagnetic layer.

8. The memory according to claim 1 , further comprising a control circuit configured to select an j-th (2≦j≦n−1) ferromagnetic layer from the first to the n-th ferromagnetic layer of the at least one cell string, and to cause first write current to flow from the j-th ferromagnetic layer to one of the first to an (j−1)-th ferromagnetic layer via the j-th semiconductor region, and to cause second write current to flow between the j-th ferromagnetic layer and one of an (j+1)-th to the n-th ferromagnetic layer via the j-th semiconductor region.

9. The memory according to claim 1 , wherein one of the first to the n-th ferromagnetic layer is greater in volume than the others.

10. The memory according to claim 1 , wherein n is equal to 4 or more.

11. A spin transistor memory comprising at least one cell string,
the at least one cell string including:
first to n-th (n≧3) semiconductor regions of a first conductivity type disposed in a semiconductor layer;
n−1 gates, of which an i-th (i=1, . . . , n−1) gate is disposed above the semiconductor layer between an i-th semiconductor region and an (i+1)-th semiconductor region; and
n ferromagnetic layers, of which an i-th (i=1, . . . , n) ferromagnetic layer disposed on the i-th semiconductor region,

wherein a direction of magnetization of one of the first to the n-th ferromagnetic layer is fixed in a predetermined direction, and directions of magnetization of the others are variable, and
wherein when m is at least one of 1, . . . , n−1, a m-th and (m+1)-th ferromagnetic layers having variable magnetization directions exist in the n ferromagnetic layers.

12. The memory according to claim 11 , wherein n is equal to 4 or more.

13. The memory according to claim 11 , wherein:
one of the first to the n-th ferromagnetic layer is a k-th (1≦k≦n−1) ferromagnetic layer, directions of magnetization of a (k+1)-th ferromagnetic layer to the n-th ferromagnetic layer are expressed as a bit of 0 or 1, depending on whether the directions of magnetization are parallel to or antiparallel to a direction of magnetization of the k-th ferromagnetic layer, and a group of bits in which the bits are arranged from that of the (k+1)-th ferromagnetic layer to that of the n-th ferromagnetic layer is set as a first code;
resistance values between adjacent ferromagnetic layers from the k-th ferromagnetic layer to the n-th ferromagnetic layer are expressed as a bit of 0 or 1, a group of bits in which the bits are arranged from that of the k-th ferromagnetic layer to the n-th ferromagnetic layer is set as a second code; and
a conversion from the first code to the second code is a conversion from a binary code to a Gray code.

14. The memory according to claim 13 , wherein the one of the first to n-th ferromagnetic layer is a first ferromagnetic layer.

15. The memory according to claim 13 , wherein the first code is an input value inputted to the cell string, and the second code is an output value outputted from the cell string.

16. The memory according to claim 15 , further comprising a converter configured to convert a Gray code to a binary code, the converter being disposed on an output side of the cell string and receiving the output value as an input.

17. The memory according to claim 15 , further comprising a converter configured to convert a Gray code to a binary code, the converter being disposed on an input side of the cell string, and the cell string receiving an output of the converter as the input value.

18. The memory according to claim 11 , further comprising a nonmagnetic layer disposed between the i-th semiconductor region and the i-th ferromagnetic layer.

19. The memory according to claim 11 , further comprising a control circuit configured to select an j-th (2≦j≦n−1) ferromagnetic layer from the first to the n-th ferromagnetic layer of the at least one cell string, and to cause first write current to flow from the j-th ferromagnetic layer to one of the first to an (j−1)-th ferromagnetic layer via the j-th semiconductor region, and to cause second write current to flow between the i-th ferromagnetic layer and one of an (j+1)-th to the n-th ferromagnetic layer via the j-th semiconductor region.

Assignees

• Toshiba Kk

Inventors

• Sugiyama Hideyuki
• Ishikawa Mizue
• Inokuchi Tomoaki
• Saito Yoshiaki

Classifications

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• H01L29/66984

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/165

  Auxiliary circuits · CPC title

• H03K19/18

  using galvano-magnetic devices, e.g. Hall-effect devices · CPC title