Dynamically updating logical identifiers of cores of a processor

Patent metadata

Field	Value
Publication number	US-9842082-B2
Application number	US-201514633455-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Feb 27, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage separate from the first storage to store a logical identifier associated with the core;
a plurality of thermal sensors to measure a temperature at a corresponding location of the processor;
a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread in execution on the first core to be migrated from the first core to the second core transparently to an operating system;
a mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the dynamic core identifier logic is to update an entry of the mapping table associated with the second core responsive to the dynamic remapping of the first logical identifier to the second core to store the first logical identifier in the entry associated with the second core; and
an input/output (I/O) interface coupled to the plurality of cores, wherein the I/O interface is associated with a second mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the dynamic core identifier logic is to communicate the update to the entry of the mapping table to the I/O interface to enable the second mapping table to be updated.

2. The processor of claim 1 , wherein the dynamic core identifier logic is to dynamically remap the first logical identifier based on at least one of a usage history and aging information of the first core.

3. The processor of claim 2 , wherein the dynamic core identifier logic is to dynamically remap the first logical identifier based on a power consumption level of the first core.

4. The processor of claim 1 , wherein the dynamic core identifier logic is to provide the first logical identifier to the second core to enable the second core to store the first logical identifier in the second storage of the second core.

5. The processor of claim 4 , wherein the second core is to thereafter obtain a context of the first thread from a retention storage and continue execution of the first thread.

6. The processor of claim 1 , wherein each of the physical identifiers for each of the plurality of cores is unique and static.

7. The processor of claim 1 , wherein the dynamic core identifier logic is to dynamically remap the first logical identifier to migrate the first thread from the first core to the second core when the first core has a higher power consumption level than the second core and a subset of the plurality of cores are active, the first core to be placed in an inactive state after the dynamic remap.

8. The processor of claim 1 , wherein the dynamic core identifier logic is to dynamically remap the first logical identifier to migrate the first thread from the first core to the second core when the second core is to operate at a higher turbo mode frequency than the first core, wherein the first thread comprises a high priority thread to execute on a single core.

9. The processor of claim 1 , wherein the dynamic core identifier logic is to dynamically remap the first logical identifier to migrate the first thread from the first core to the second core when temperature information associated with a first region including the first core exceeds a threshold, and temperature information associated with a second region including the second core is less than the threshold.

10. A system comprising:
a processor having:
a plurality of cores, each of the plurality of cores including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core;
a power controller, based at least in part on a temperature associated with a first core, to dynamically remap a first logical identifier from association with the first core to association with a second core while the first core and the second core are in a low power state, to cause a first thread in execution on the first core to be migrated from the first core to the second core transparently to an operating system;
a first mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association for a core;
an input/output (I/O) interface to couple to one or more devices and to provide an incoming message to a selected core; and
a second mapping table coupled to the I/O interface including a second plurality of entries each to store a logical identifier-to-physical identifier association for a core, wherein the power controller is to dynamically update a first entry of the first mapping table to associate the first logical identifier with the second core and to cause a dynamic update to a corresponding entry of the second mapping table to associate the first logical identifier with the second core; and a dynamic random access memory (DRAM) coupled to the processor.

11. The system of claim 10 , wherein the processor comprises a storage to store a plurality of entries each associated with a core and including a plurality of characterization values for the core, wherein at least some of the plurality of cores have a different characterization value for a first operating parameter, based on manufacturing variation.

12. The system of claim 10 , wherein the power controller is to cause the second core to exit the low power state and thereafter provide the first logical identifier to the second core for storage in the second storage of the second core.

13. The system of claim 12 , wherein the second core is to access context information of the first thread from a shared cache memory and resume execution of the first thread, based at least in part on the first logical identifier.

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Sistla Krishnakanth V
• Sotomayor Guy G
• Henroid Andrew D
• Gough Robert E
• Schiff Tod F

Classifications

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/45541

  Bare-metal, i.e. hypervisor runs directly on hardware · CPC title

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title