Semiconductor system including replacement storage unit

Patent metadata

Field	Value
Publication number	US-9842035-B2
Application number	US-201615236287-A
Country	US
Kind code	B2
Filing date	Aug 12, 2016
Priority date	Mar 24, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

First claim

What is claimed is:

1. A semiconductor system comprising:
one or more core chips including a plurality of memory banks;
one or more replacement storage units; and
a base chip suitable for:
first detecting a memory bank having an access frequency that satisfies a first condition,
second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and
replacing the second detected memory bank with one among the replacement storage units,
wherein the one or more core chips comprise one or more channels including one or more memory banks among the plurality of memory banks, and the one or more channels are independently controlled, and
wherein the base chip is suitable for setting a channel that all the included memory banks are replaced with the replacement storage units among the one or more channels to a power down mode.

2. The semiconductor system of claim 1 , wherein the first condition is a condition in which the access frequency is greater than a reference access frequency.

3. The semiconductor system of claim 1 , wherein the first condition is a condition in which the access frequency is less than a reference access frequency.

4. The semiconductor system of claim 1 , wherein the second condition is a condition in which the utilization rate of the first detected memory bank is greater than a replacement utilization threshold rate.

5. The semiconductor system of claim 1 , wherein the second condition is a condition in which the utilization rate of the first detected memory bank is less than a replacement utilization threshold rate.

6. The semiconductor system of claim 1 , wherein each of the plurality of memory banks comprise a plurality of word lines, and
the utilization rate of the first detected memory bank is a ratio of the number of word lines in a used state over the total number of the plurality of word lines of the first detected memory bank.

7. The semiconductor system of claim 1 , wherein the base chip is suitable for monitoring whether or not the plurality of memory banks in one or more core chips are accessed, and is suitable for performing the first detection using a monitoring result.

8. The semiconductor system of claim 1 , wherein the base chip is suitable for controlling data of the second detected memory bank to be transmitted to and stored in the replacement storage unit.

9. The semiconductor system of claim 1 , wherein if the access command to the second detected memory bank is inputted while the data of the second detected memory bank is transmitted to and stored in the replacement storage unit, the base chip is suitable for controlling the replacement storage unit to be accessed when a word line which is an object of an access command is in a replacement state that all the data of the word lines are stored in the replacement storage unit and suitable for controlling the second detected memory bank to be accessed when the word line which is the object of the access command is in a non-replacement state that all the data of the word lines are not stored in the replacement storage unit.

10. The semiconductor system of claim 9 , wherein the base chip is suitable for controlling a transmission and storage of the data to be performed at the latency time corresponding to the access command when the access command to the second detected memory bank is inputted while the data of the second detected memory bank is transmitted to and stored in the replacement storage unit.

11. The semiconductor system of claim 1 , wherein the base chip is suitable for accessing the replacement storage unit which replaces a first memory bank or suitable for interrupting the access command in response to an access command, which includes one or more commands among an active command, a precharge command, a refresh command, a write command and a read command, corresponding to a replacement-target bank which is replaced with the replacement storage unit among the plurality of memory banks.

12. The semiconductor system of claim 11 , wherein the base chip is suitable for interrupting the access command when the access command is the active command, the precharge command or the refresh command, and suitable for accessing the replacement storage units which replaces the replacement-target bank when the access command is the write command or the read command.

13. The semiconductor system of claim 1 , wherein the base chip is suitable for third-detecting whether or not a first detected replacement-target bank satisfies a third condition when the first detected memory bank is a replacement-target bank, and suitable for restoring the replacement storage units which replaces a third-detected replacement-target bank to the third-detected replacement-target bank.

14. The semiconductor system of claim 13 , wherein the third condition is a condition in which the utilization rate of the first detected replacement-target bank has to be greater than a restoration utilization threshold rate.

15. The semiconductor system of claim 13 , wherein the third condition is a condition in which the utilization rate of the first detected replacement-target bank has to be less than a restoration utilization threshold rate.

16. The semiconductor system of claim 13 , wherein the base chip is suitable for controlling data of the replacement storage units which replaces the third-detected replacement-target bank to be transmitted to and stored in the third-detected replacement-target bank.

17. The semiconductor system of claim 13 , wherein if the access command to the third-detected replacement-target bank is input while data of the replacement storage units which replaces the third-detected replacement-target bank is transmitted to and stored in the third-detected replacement-target bank, the base chip is suitable for controlling the replacement storage units to be accessed when a word line which is an object of an access command is in a replacement state that all the data of the word lines are stored in the replacement storage units and suitable for controlling the third-detected replacement-target bank to be accessed when the word line which is the object of the access command is in a non-replacement state that all the data of the word lines are not stored in the replacement storage units.

18. The semiconductor system of claim 17 , wherein the base chip is suitable for controlling a transmission and storage of the data to be performed at the latency time corresponding to the access command when the access command to the third-detected replacement-target bank is input while the data of the replacement storage units which replaces the third-detected replacement-target bank is transmitted to and stored in the third-detected replacement-target bank.

19. The semiconductor system of claim 1 , wherein the base chip comprises:
a first control unit suitable for generating one or more control signals by receiving an access command, suitable for transmitting the one or more control signals to the one or more core chips, and suitable for monitoring whether or not the plurality of memory banks in the one or more core chips are accessed;
a second control unit suitable for controlling data transmitting between the one or more replacement storage units and the plurality of memory banks in the one or more core chips, and between the one or more replacement storage units and the first control unit; and
a monitoring unit suitable for performing the first detecting by monitoring whether or not the plurality of memory banks in the one or more core chips are

Assignees

• Sk Hynix Inc

Inventors

• Lee Kyung-Min
• Song Young-Ook
• Kim Ki-Joong
• Kim Yong-Ju
• Kwon Jung-Hyun
• JO Sang-Gu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C29/702 Primary

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title