Generating soft read values using multiple reads and/or bins

Patent metadata

Field	Value
Publication number	US-9842023-B2
Application number	US-201615007996-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Jan 27, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value.

First claim

What is claimed is:

1. A system for generating a soft read value, comprising:
a storage read interface configured to read at a read threshold; and
a soft information generator configured to:
obtain an old bin associated with a cell;
map the old bin to a new bin; and
assign, to the cell, a soft read value corresponding to the new bin.

2. The system of claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system of claim 1 further comprising solid state storage, wherein the storage read interface is configured to read the solid state storage.

4. The system of claim 1 , wherein the soft information generator is configured to map by:
determining if the read threshold falls in a given bin; and
in the event the read threshold falls in the given bin, dividing the given bin in half at the read threshold.

5. The system of claim 4 , wherein the soft information generator is further configured to map by: in the event the read threshold does not fall in the given bin, mapping the given bin to a new bin that preserves the left bin boundary and the right bin boundary of the given bin.

6. The system of claim 1 , wherein the storage read interface is configured to read a single level cell (SLC) storage.

7. The system of claim 1 , wherein the storage read interface is configured to read a multi-level cell (MLC) storage.

8. The system of claim 7 further comprising a read threshold generator configured to generate a left most significant bit (MSB) read threshold and a right MSB read threshold, wherein the read threshold generator is configured to:
during a first read period, hold the left MSB read threshold fixed and permit the right MSB read threshold to vary; and
during a second read period, permit the left MSB read threshold to vary and hold the right MSB read threshold fixed.

9. The system of claim 7 further comprising a read threshold generator configured to generate a left most significant bit (MSB) read threshold and a right MSB read threshold, wherein the read threshold generator is configured to let the left MSB read threshold and the right MSB read threshold simultaneously vary.

10. A method for generating a soft read value, comprising:
using a storage read interface to read at a read threshold;
obtaining an old bin associated with a cell;
using a soft information generator to map the old bin to a new bin; and
using the soft information generator to assign, to the cell, a soft read value corresponding to the new bin.

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Tang Xiangyu
• Lee Frederick K H
• Bellorado Jason
• Subramanian Arunkumar
• Zeng Lingqi

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title