Efficient bin labeling schemes for tracking cells in solid state storage devices

Patent metadata

Field	Value
Publication number	US-9390002-B1
Application number	US-201314065258-A
Country	US
Kind code	B1
Filing date	Oct 28, 2013
Priority date	Jan 23, 2013
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Information associated with a read to solid state storage is received, including a read number and a read value. The read value is written to a location in a cell and bin map, wherein (1) the location in the cell and bin map corresponds to the read number and (2) the cell and bin map tracks, for each cell in a group of cells, which bin out of a plurality of bins a given cell falls into.

First claim

What is claimed is:

1. A system, comprising:
a map updater configured to:
receive information associated with a read to solid state storage, including a read number and a read value;
write the read value to a location in a cell and bin map, wherein (1) the location in the cell and bin map corresponds to the read number and (2) the cell and bin map tracks, for each cell in a group of cells, which bin out of a plurality of bins a given cell falls into;
determine if the read number matches a number of bits available for a direct write bin label; and
in the event it is determined that the read number matches the number of bits, sum a number of times a value being counted occurs in the direct write bin label and write the sum over the direct write bin label; and
a memory configured to store the cell and bin map.

2. The system of claim 1 , wherein the map updater is implemented using a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system of claim 1 , wherein the solid state storage includes NAND Flash.

4. The system of claim 1 , wherein the solid state storage includes one or more of the following: a single-level cell which is configured to store a single bit, a multi-level cell which is configured to store two bits, a triple-level cell (TLC) which is configured to store three bits, or a quad-level cell (QLC) which is configured to store four bits.

5. The system of claim 1 , wherein:
the solid state storage includes a multi-level cell which is configured to store two bits; and
a first most significant bit (MSB) read threshold and a second MSB read threshold are constrained to mirror each other, such that one or more bin labels which result are symmetric.

6. The system of claim 1 , wherein the map updater is further configured to:
determine if the read value matches a value being counted; and
in the event it is determined that the read value matches the value being counted, increment a count in the cell and bin map.

7. The system of claim 6 further comprising a soft read value generator, wherein the soft read value generator is configured to input: (1) a mode signal associated with indicating a direct write bin labeling mode and an accumulative bin labeling mode and (2) cell and bin map information which in the bin labeling mode includes one or more direct write bin labels and in the accumulative bin labeling mode includes one or more accumulative bin labels.

8. A system, comprising:
a map updater configured to:
receive information associated with a read to solid state storage, including a read value;
determine if the read value matches a value being counted; and
in the event it is determined that the read value matches the value being counted, increment a count in a cell and bin map, wherein the cell and bin map tracks, for each cell in a group of cells, which bin out of a plurality of bins a given cell falls into;
determine if the read number matches a number of bits available for a direct write bin label; and
in the event it is determined that the read number matches the number of bits, sum a number of times a value being counted occurs in the direct write bin label and write the sum over the direct write bin label; and
a memory configured to store the cell and bin map.

9. The system of claim 8 , wherein the value being counted is a 1.

10. The system of claim 8 , wherein the map updater is implemented using a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

11. The system of claim 8 , wherein the solid state storage includes NAND Flash.

12. The system of claim 8 , wherein the solid state storage includes one or more of the following: a single-level cell which is configured to store a single bit, a multi-level cell which is configured to store two bits, a triple-level cell (TLC) which is configured to store three bits, or a quad-level cell (QLC) which is configured to store four bits.

13. The system of claim 8 , wherein:
the solid state storage includes a multi-level cell which is configured to store two bits; and
a first most significant bit (MSB) read threshold and a second MSB read threshold are constrained to mirror each other, such that one or more bin labels which result are symmetric.

14. A method, comprising:
receiving information associated with a read to solid state storage, including a read number and a read value;
using a processor to write the read value to a location in a cell and bin map, wherein (1) the location in the cell and bin map corresponds to the read number and (2) the cell and bin map tracks, for each cell in a group of cells, which bin out of a plurality of bins a given cell falls into;
determining if the read number matches a number of bits available for a direct write bin label; and
in the event it is determined that the read number matches the number of bits, summing a number of times a value being counted occurs in the direct write bin label and writing the sum over the direct write bin label.

15. The method of claim 14 , wherein the method is performed using a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

16. The method of claim 14 , wherein the solid state storage includes NAND Flash.

17. The method of claim 14 , wherein the solid state storage includes one or more of the following: a single-level cell which is configured to store a single bit, a multi-level cell which is configured to store two bits, a triple-level cell (TLC) which is configured to store three bits, or a quad-level cell (QLC) which is configured to store four bits.

18. A method, comprising:
receiving information associated with a read to solid state storage, including a read value;
using a processor to determine if the read value matches a value being counted;
in the event it is determined that the read value matches the value being counted, using the processor to increment a count in a cell and bin map, wherein the cell and bin map tracks, for each cell in a group of cells, which bin out of a plurality of bins a given cell falls into;
determining if the read number matches a number of bits available for a direct write bin label; and
in the event it is determined that the read number matches the number of bits, summing a number of times a value being counted occurs in the direct write bin label and writing the sum over the direct write bin label.

19. The method of claim 18 , wherein the method is performed using a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

20. The method of claim 18 , wherein the solid state storage includes NAND Flash.

21. The method of claim 18 , wherein the solid state storage includes one or more of the following: a single-level cell which is configured to store a single bit, a multi-level cell which is configured to store two bits, a triple-level cell (TLC) which is configured to store three bits, or a quad-level cell (QLC) which is configured to store four bits.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hsiao-Heng
• Zeng Lingqi
• Lee Frederick K H
• Bellorado Jason

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/3431

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G06F12/0207 Primary

  with multidimensional access, e.g. row/column, matrix · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title