Method and apparatus for execution mode selection

Patent metadata

Field	Value
Publication number	US-9841997-B2
Application number	US-201514750212-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An apparatus and method for performing high performance instruction emulation. One embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-power instructions if the number of high-power instructions are below the specified threshold.

First claim

What is claimed is:

1. A processor to process an instruction set including high-power and standard instructions comprising:
an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold;
an execution mode selection module to select a native execution mode for the high-power instructions if the number of high-power instructions are above the specified threshold and to select an emulated execution mode for the high-power instructions if the number of high-power instructions are below the specified threshold, and
a decoder to decode the high-power instructions into low-power microoperations in the emulated execution mode.

2. The processor as in claim 1 wherein if the number of high-power instructions within a window is equal to the threshold, then the execution mode selection module is configured to select either native execution or emulated execution of the high-power instructions.

3. The processor as in claim 1 wherein the window comprises a specified amount of time and the threshold comprises a threshold number of high-power instructions within the specified amount of time or wherein the window comprises a specified number of instructions and the threshold comprises a threshold number of high-power instructions within the specified number of instructions.

4. The processor as in claim 1 , wherein the decoder is to decode the high-power instructions into a first set of microoperations responsive to the execution mode selection module determining that the number of high-power instructions are below the specified threshold and to decode the high-power instructions into a second set of microoperations responsive to the execution mode selection module determining that the number of high-power instructions are above the specified threshold.

5. The processor as in claim 4 wherein the first set of microoperations consume relatively less power than the second set of microoperations.

6. The processor as in claim 5 wherein the second set of microoperations complete execution of a corresponding macroinstruction more quickly than the first set of microoperations.

7. The processor as in claim 1 wherein the high-power instructions include wide single instruction multiple data (SIMD) instructions, certain types of floating point instructions, and instructions which utilize hardware offload engines.

8. The processor as in claim 1 wherein a high-power instruction comprises an instruction which natively consumes more power and/or is executed at a different voltage or frequency than a standard instruction.

9. The processor as in claim 1 wherein a performance overhead is associated with entering and exiting the native execution mode and wherein the threshold is set in view of the performance overhead.

10. The processor as in claim 9 wherein the performance overhead comprises an amount of time required to enter and/or exit the native execution mode.

11. A method to process an instruction set including high-power and standard instructions comprising:
determining whether a number of high-power instructions within a specified window are above or below a specified threshold;
selecting a native execution mode for the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution mode for the high-power instructions if the number of high-power instructions are below the specified threshold; and
decoding the high-power instructions into low-power microoperations in the emulated execution mode.

12. The method as in claim 11 wherein if the number of high-power instructions within a window is equal to the threshold, then selecting either native execution or emulated execution of the high-power instructions.

13. The method as in claim 11 wherein the window comprises a specified amount of time and the threshold comprises a threshold number of high-power instructions within the specified amount of time or wherein the window comprises a specified number of instructions and the threshold comprises a threshold number of high-power instructions within the specified number of instructions.

14. The method as in claim 13 wherein the decoding comprises:
decoding the high-power instructions into a first set of microoperations responsive to determining that the number of high-power instructions are below the specified threshold and decoding the high-power instructions into a second set of microoperations responsive to determining that the number of high-power instructions are above the specified threshold.

15. The method as in claim 14 wherein the first set of microoperations consume relatively less power than the second set of microoperations.

16. The method as in claim 15 wherein the second set of microoperations complete execution of a corresponding macroinstruction more quickly than the first set of microoperations.

17. The method as in claim 11 wherein the high-power instructions include wide single instruction multiple data (SIMD) instructions, certain types of floating point instructions, and instructions which utilize hardware offload engines.

18. The method as in claim 11 wherein a high-power instruction comprises an instruction which natively consumes more power and/or is executed at a different voltage or frequency than a standard instruction.

19. The method as in claim 11 wherein a performance overhead is associated with entering and exiting the native execution mode and wherein the threshold is set in view of the performance overhead.

20. The method as in claim 19 wherein the performance overhead comprises an amount of time required to enter and/or exit the native execution mode.

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Fleming Kristoffer D
• Gorbatov Eugene
• Gough Robert E
• Sistla Krishnakanth V

Classifications

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/4893 Primary

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title