Processor with a program counter increment based on decoding of predecode bits

Patent metadata

Field	Value
Publication number	US-9841978-B2
Application number	US-201113137134-A
Country	US
Kind code	B2
Filing date	Jul 22, 2011
Priority date	Sep 13, 2010
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

First claim

What is claimed is:

1. A processor, comprising:
an instruction cache configured to store a group of instructions and simultaneously output said group of instructions;
an instruction selector configured to simultaneously receive said group of instructions from said instruction cache and to multiplex said group of instructions by use of one or more multiplexers to select an instruction from said group of instructions;
a coprocessor configured to receive one or more instructions from said instruction cache based on a simultaneously issuable instruction count field of said group of instructions, and based on said group of instructions including at least one coprocessor instruction, and to decode said one or more instructions based on a first decoding process, wherein said one or more instructions after said first decoding process are coprocessor-decoded one or more instructions, and wherein said simultaneously issuable instruction count field indicates a number of instructions to be issued to said coprocessor;
an instruction decoder configured to receive said selected instruction from said instruction selector based on said selected instruction being a processor instruction, and to decode said selected instruction based on a second decoding process, wherein said selected instruction after said second decoding process is a processor-decoded instruction; and
a sequential execution portion configured to receive said processor-decoded instruction from said instruction decoder and to execute said processor-decoded instruction, wherein said coprocessor is configured to execute said coprocessor-decoded one or more instructions.

2. The processor according to claim 1 , wherein said processor is further configured to decode and execute another instruction of said group of instructions.

3. The processor according to claim 1 , wherein said group of instructions is a group of fixed-length instructions.

4. The processor according to claim 1 , wherein said processor-decoded instruction and said coprocessor-decoded one or more instructions are simultaneously executable.

5. The processor according to claim 1 , further comprising:
a specific field decoder configured to fetch a specific field from said group of instructions and to convert said specific field into an increment value.

6. The processor according to claim 5 , wherein said specific field includes said simultaneously issuable instruction count field.

7. The processor according to claim 5 , wherein a program counter is incremented by an integer amount that corresponds to said increment value.

8. The processor according to claim 7 , wherein a value of said integer amount is variable.

9. The processor according to claim 7 , wherein said program counter indicates a memory address, wherein said memory address identifies a location in said instruction cache where a first instruction of said group of instructions is stored.

10. The processor according to claim 7 , wherein said increment value is set prior to said group of instructions being decoded.

11. The processor according to claim 10 , wherein said increment value is set before said coprocessor is configured to decode said one or more instructions based on said first decoding process.

12. The processor according to claim 7 , wherein a number of instructions in said group of instructions is readable from said instruction cache in a cycle.

13. The processor according to claim 12 , wherein said number of instructions is at least 1.

14. The processor according to claim 1 , wherein said first decoding process is configured to decode said one or more instructions.

15. The processor according to claim 14 , wherein said second decoding process is configured to decode said selected instruction.

16. The processor according to claim 1 , wherein said instruction cache includes an instruction cache tag memory configured to hold a tag part of instruction addresses.

Assignees

• Hanaki Hirokazu
• Takashima Satoshi
• Sony Corp

Inventors

• Hanaki Hirokazu
• Takashima Satoshi

Classifications

• G06F9/321 Primary

  Program or instruction counter, e.g. incrementing · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title