Multithreading in vector processors

Patent metadata

Field	Value
Publication number	US-2016291978-A1
Application number	US-201615066311-A
Country	US
Kind code	A1
Filing date	Mar 10, 2016
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

First claim

What is claimed is:

1 . A system comprising:
a processor having a vector processing mode and a multithreading mode, the processor being a vector processor and being configured to operate on one thread per cycle in the multithreading mode, and the processor comprising:
one or more program counter registers together comprising a plurality of program counters, each program counter register of the one or more program counter registers being vectorized into a corresponding subset of the plurality of program counters, and each program counter in the plurality of program counters of one or more program counter registers representing a distinct corresponding thread of a plurality of threads;
wherein the number of threads in the plurality of threads is limited by the number of program counters in the plurality of program counters of the one or more program counter registers;
the processor configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle. an instruction buffer comprising a plurality of instructions; wherein a first program counter in the plurality of program counters references a first instruction in the instruction buffer for execution by the processor in a first thread of the plurality of threads; wherein a second program counter in the plurality of program counters references a second instruction in the instruction buffer for execution by the processor in a second thread of the plurality of threads; and wherein the first instruction differs from the second instruction.

Assignees

• IBM

Inventors

• Evangelinos Constantinos
• Kim Changhoan
• Nair Ravi

Classifications

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F15/8053

  Vector processors · CPC title

• G06F9/321

  Program or instruction counter, e.g. incrementing · CPC title

• G06F15/8076 Primary

  Details on data register access · CPC title

• G06F15/8084

  Special arrangements thereof, e.g. mask or switch · CPC title