Lock free streaming of executable code data

Patent metadata

Field	Value
Publication number	US-9841976-B2
Application number	US-201615257794-A
Country	US
Kind code	B2
Filing date	Sep 6, 2016
Priority date	Jul 27, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page.

First claim

What is claimed is:

1. A method of writing a long opcode that overlaps two or more atomically writable blocks of memory, comprising:
atomically writing, by a computing device, a latter portion of the long opcode to a second atomically writable block of memory of the computing device, the latter portion of the long opcode being after a prior portion of the long opcode; and
atomically writing, by the computing device, the prior portion of the long opcode to a first atomically writable block of memory of the computing device;
wherein the atomically writing the prior portion is performed after the atomically writing the latter portion; and
wherein further the second atomically writeable block of memory comprises both debug break point opcodes and the latter portion of the long opcode after the atomically writing the latter portion.

2. The method of claim 1 , further comprising:
appending, by the computing device, the debug break point opcodes to the latter portion of the long opcode to create a full standard block of memory.

3. The computer-implemented method of claim 1 , further comprising:
writing, by the computing device, a previous opcode and the prior portion of the long opcode to the first memory block.

4. The method of claim 1 , wherein prior to the atomically writing the latter portion of the long opcode, the first atomically writable block of memory contains a debug break point opcode at an address the prior portion of the long opcode is to be written to.

5. The method of claim 1 , wherein prior to the atomically writing the latter portion of the long opcode, ensuring the two or more atomically writable blocks of memory contain debug break point opcodes.

6. The method of claim 1 , further comprising:
retrying, by the computing device, a fault mechanism after writing the prior portion of the long opcode, the fault mechanism having been triggered by a debug break point opcode that was present in the first atomically writable block of memory at an address the prior portion of the long opcode was subsequently written to.

7. The method of claim 6 , wherein the fault mechanism is either a stream fault interceptor or an operating system fault mechanism.

8. The method of claim 1 , wherein the first atomically writable block of memory precedes the second atomically writable block of memory.

9. A computer system, comprising:
one or more processors;
system memory; and
one or more computer-readable storage media having stored thereon computer-executable instructions that, when executed by the one or more processors, cause the processors to:
initialize blocks of memory, prior to storing new opcodes in the block of memory, by writing debug break point opcodes to all memory locations of the blocks of memory being initialized, the debug break point opcodes faulting to a fault mechanism; and
subsequently write the new opcodes to the initialized memory by overwriting at least some of the debug break point opcodes.

10. The computer system of claim 9 , wherein the one or more computer-readable storage media comprise further computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to:
identify when a long opcode will overlap two or more standard blocks of memory;
write a latter portion of the long opcode to a second memory block, the latter portion of the long opcode being after a prior portion of the long opcode; and
write the prior portion of the long opcode to a first memory block after the writing of the latter portion.

11. The computer system of claim 10 , the processor further operating to:
append debug break point opcodes to the latter portion of the long opcode in to create a full standard block of memory.

12. The computer system of claim 10 , the processor further operating to:
write a previous opcode and the prior portion of the long opcode to the first memory block.

13. The computer system of claim 9 , wherein the fault mechanism is a stream fault interceptor operating to identify when a requested data page is not available.

14. The computer system of claim 13 , wherein the stream fault interceptor identifies when the requested data page is not available by differentiating between a breakpoint that occurs as part of stream faulting, in which case the stream fault interceptor identifies the requested data page as not available, and a breakpoint associated with a debugger or application, in which case the stream fault interceptor passes the breakpoint back to the debugger or the application.

15. The computer system of claim 14 , wherein the stream fault interceptor performs the differentiating based on a table that identifies boundaries between each opcode.

16. The computer system of claim 9 , further comprising:
a page tracker maintaining a table that identifies boundaries between each opcode.

17. The computer system of claim 9 , wherein the one or more computer-readable storage media comprise further computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to:
append the debug break point opcodes to an opcode to create a full standard block of memory;
wherein the writing the opcodes comprises atomically writing standard blocks of memory.

18. A computer system, comprising:
one or more processors; and
computer-readable data storage storing computer-executable instructions that when executed by at least one processor of the one or more processors causes the computer system to:
receive an exception notification that a breakpoint has been encountered at a memory location requested by a memory access request;
differentiate between a breakpoint that occurs as part of stream faulting and a breakpoint associated with a debugger or application;
retry the memory access request after a writing of data to the memory location completes if the differentiating determines that the breakpoint is a breakpoint that occurs as part of stream faulting; and
pass the exception notification back to the debugger or the application if the differentiating determines that the breakpoint is the associated with the debugger or the application.

19. The computer system of claim 18 , wherein blocks of memory are initialized by writing debug break point opcodes to all memory locations prior to writing opcodes to the initialized memory by overwriting at least some of the debug break points, the debug break point opcodes triggering the fault.

20. The computer system of claim 19 , wherein the differentiating comprises referencing a table that identifies boundaries between each of the opcodes written to the initialized memory.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Reierson Kristofer

Classifications

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F9/30149 Primary

  of variable length instructions · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title