Computer program instruction analysis

Patent metadata

Field	Value
Publication number	US-9600284-B2
Application number	US-201514929861-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Apr 19, 2012
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Disclosed is a method of analysis of a computer program instruction for use in a central processing unit having a decoding unit. The method includes receiving an address of an instruction to be analyzed, fetching said instruction stored at said address, decoding by a decoding unit associated with the central processing unit, the fetched instruction, and returning the results of said decoding of said fetched instruction. The decoded results may be returned as a data block stored in memory associated with the central processing unit or in one or more registers of the central processing unit. The decoded results may include the type of the instruction and/or the instruction length. The method may further include analyzing the decoded results to determine whether the instruction may be replaced with one of a trap or a break point.

First claim

The invention claimed is:

1. A method of analysis of a computer program instruction for use in a central processing unit (CPU) comprising a decoding unit, the method comprising:
receiving, with the CPU, an address of an instruction stored in memory to be analyzed;
fetching, with the CPU, the instruction stored at the address;
decoding, with the decoding unit, the fetched instruction;
generating, with the decoding unit, results of the decode of the fetched instruction as a data block that is not passed from the decoding unit to an arithmetic unit within the CPU nor is passed from the decoding unit to a memory access unit within the CPU, the data block comprising: a fetched instruction length value within an instruction length field, a fetched instruction type value within an instruction type field, a privilege flag value within a privilege flag field that indicates whether the fetched instruction is privileged, a fault flag value within a fault flag field that indicates whether the fetched instruction can fault, a memory access flag value within a memory access flag field that indicates whether the fetched instruction can access memory, and an interrupt flag value within an interrupt flag field that indicates whether the fetched instruction can cause an interrupt;
passing, with the decoding unit, the data block to a register within the CPU which stores the data block; and
analyzing, the instruction with an analysis program called by the CPU, by accessing the data block from the register to determine whether the instruction may be replaced with one of a trap or a break point.

Assignees

• IBM

Inventors

• Gilbert David A

Classifications

• G06F9/30076 Primary

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F11/3636

  by tracing the execution of the program · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title