Machine learning-based universal software component identification
US-12175241-B1 · Dec 24, 2024 · US
US9841958B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9841958-B2 |
| Application number | US-97720710-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2010 |
| Priority date | Dec 23, 2010 |
| Publication date | Dec 12, 2017 |
| Grant date | Dec 12, 2017 |
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A high level programming language provides extensible data parallel semantics. User code specifies hardware and software resources for executing data parallel code using a compute device object and a resource view object. The user code uses the objects and semantic metadata to allow execution by new and/or updated types of compute nodes and new and/or updated types of runtime libraries. The extensible data parallel semantics allow the user code to be executed by the new and/or updated types of compute nodes and runtime libraries.
Opening claim text (preview).
What is claimed is: 1. A device, comprising: at least one processor and a memory, the at least one processor configured to: generate, during runtime execution of user code, a compute device object and a resource view object in accordance with directives in the user code, the compute device object generated with a device level specified in the user code, the device level indicating a type of compute node, the resource view object generated with a first resource level specified in the user code, the first resource level indicating a type of runtime library for use in execution of the user code; obtain an annotation associated with a code portion in the user code, the annotation identifying the code portion as a data parallel function and includes a second resource level indicating a type of runtime library for use in execution of the code portion, wherein the first resource level differs from the second resource level; and execute the data parallel function using a compute node corresponding to the device level and the first resource level when the first resource level has fewer or same semantic restrictions as the second resource level. 2. The device of claim 1 , wherein the first resource level specifies native, the first resource level indicates that semantic restrictions of the data parallel function conform to semantics of a general purpose programming language of the user code. 3. The device of claim 1 , wherein the at least one processor is further configured to: detect that the device level is custom in the compute device object; and use a custom data parallel function in response to detecting that the device level is custom, wherein the custom data parallel function includes a custom implementation of the data parallel function for execution on a new and/or updated type of compute node. 4. The device of claim 1 , wherein the at least one processor is further configured to: generate a call-site implementation for the compute node using a call-site abstraction function. 5. The device of claim 1 , wherein the user code is written in a programming language with data parallel extensions. 6. The device of claim 1 , wherein the user code is written in a high level data parallel programming language. 7. The device of claim 1 , wherein the one or more data parallel compute nodes include at least one graphics processing unit. 8. The device of claim 1 , wherein the at least one processor is further configured to: detect that the device level is custom in the compute device object; and use a custom compute device function in response to detecting that the device level is custom, wherein the custom device function includes semantic metadata that specifies a new and/or updated type of compute node. 9. A method performed by at least one processor in a computer system, the method comprising: associating at runtime a compute device object and a resource view object in accordance with directives in an application, the application includes a data parallel function, the data parallel function for execution on one or more compute nodes, the compute device object including a device level indicating a type of compute node to use in execution of the application and the resource view object including a first resource level identifying a type of runtime library to use in execution of the application; identifying an annotation applied to the data parallel function, the annotation including a second resource level indicating a type of runtime library for use with execution of the data parallel function, wherein the first resource level differs from the second resource level; and executing the data parallel function using at least one compute node associated with the device level and the first resource level when the first resource level has less or same semantic restrictions as the second resource level. 10. The method of claim 9 wherein the resource level corresponding to a resource view object is native when the data parallel function has unrestricted semantic restrictions. 11. The method of claim 9 further comprising: generating data parallel executable code to include one of a custom compute device function or a custom data parallel function in response to detecting a device level of custom, wherein the custom compute device function includes semantic metadata that specifies new and/or updated type of compute nodes, wherein the custom data parallel function includes a custom implementation of the data parallel function for execution of a new and/or updated type of compute node. 12. The method of claim 9 further comprising: generating a call-site implementation for the one or more data parallel compute nodes using a call-site abstraction function. 13. The method of claim 9 wherein the application is written in a high level general purpose programming language with data parallel extensions. 14. The method of claim 9 wherein the application is written in a high level data parallel programming language. 15. The method of claim 9 wherein the one or more compute nodes include at least one graphics processing unit. 16. The method of claim 9 wherein the one or more compute nodes include at least one general purpose processor. 17. A system, comprising: at least one processor and a memory; the memory including at least one module having processor-executable instructions that when executed by the at least one processor: generates a compute device object and a resource view object in response to data parallel source code, the compute device object specifying a device level and the resource view object specifying a resource level, the device level indicating a type of compute node for executing the data parallel source code, a first resource level indicating a type of runtime library for use in execution of the data parallel source code; obtain an annotation associated with a data parallel function in the data parallel source code, the annotation identifying a second resource level indicating a type of runtime library for use in execution of the data parallel function, wherein the first resource level differs from the second resource level; and performs the data parallel function using a compute node corresponding to the device level and the first resource level when the first resource level has same or fewer semantic restrictions of a programming language of the data parallel source code. 18. The system of claim 17 , wherein the memory includes at least one user-defined runtime library, the user-defined runtime library including a custom compute device function that includes semantic metadata identifying new and/or updated types of compute nodes. 19. The system of claim 17 , wherein the memory includes at least one user-defined runtime library, the user-defined runtime library including a custom resource view function that includes new and/or updated resource levels. 20. The system of claim 17 , wherein the memory includes at least one user defined runtime library, the user-defined runtime library including a custom data parallel function that includes a custom implementation of a call-site function.
Parallelism detection · CPC title
Semantic checking · CPC title
Parallel programming languages (G06F8/313 takes precedence) · CPC title
Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451) · CPC title
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