Method for memory consistency among heterogeneous computer components

Patent metadata

Field	Value
Publication number	US-9361118-B2
Application number	US-201414275271-A
Country	US
Kind code	B2
Filing date	May 12, 2014
Priority date	May 13, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method, computer program product, and system is described that determines the correctness of using memory operations in a computing device with heterogeneous computer components. Embodiments include an optimizer based on the characteristics of a Sequential Consistency for Heterogeneous-Race-Free (SC for HRF) model that analyzes a program and determines the correctness of the ordering of events in the program. HRF models include combinations of the properties: scope order, scope inclusion, and scope transitivity. The optimizer can determine when a program is heterogeneous-race-free in accordance with an SC for HRF memory consistency model. For example, the optimizer can analyze a portion of program code, respect the properties of the SC for HRF model, and determine whether a value produced by a store memory event will be a candidate for a value observed by a load memory event. In addition, the optimizer can determine whether reordering of events is possible.

First claim

What is claimed is:

1. A method comprising:
receiving a portion of program code, the portion having a first thread and a second thread;
identifying a store memory event associated with the first thread and a load memory event associated with the second thread, wherein the store memory event and the load memory share a same variable; and
determining, in accordance with a memory consistency model, when a program is heterogeneous-race-free due to a release synchronization event associated with the first thread and an acquire synchronization event associated with the second thread, the memory consistency model having a property of scope order, scope inclusion, scope transitivity or combination thereof, wherein the determining in accordance with the memory consistency model includes determining a correctness with regard to an ordering in program code of the release synchronization event and the acquire synchronization event and wherein the properties of the scope order, scope inclusion, and scope transitivity are defined based upon a capability of a system on which program code is being executed.

2. The method of claim 1 , wherein the scope order comprises a strong scope order or a weak scope order.

3. The method of claim 1 , wherein the scope order is a weak scope order, and the release synchronization event and the acquire synchronization event share a same scope.

4. The method of claim 1 , wherein the scope order is a strong scope order, and both scope inclusion and scope transitivity are present in the memory consistency model.

5. The method of claim 1 , wherein the scope order is a strong scope order, and scope transitivity is present in the memory consistency model.

6. The method of claim 1 , wherein the scope order is a weak scope order, and scope transitivity is present in the memory consistency model.

7. The method of claim 1 , wherein the scope order is a strong scope order, and scope inclusion is present in the memory consistency model.

8. A non-transitory computer-readable storage device having stored thereon instructions, execution of which, by a processing unit, cause the processing unit to perform operations comprising:
receiving a portion of program code, the portion having a first thread and a second thread;
identifying a store memory event associated with the first thread and a load memory event associated with the second thread, wherein the store memory event and the load memory share a same variable; and
determining, in accordance with a memory consistency model, when a program is heterogeneous-race-free due to a release synchronization event associated with the first thread and an acquire synchronization event associated with the second thread, the memory consistency model having a property of scope order, scope inclusion, scope transitivity or combination thereof, wherein the determining in accordance with the memory consistency model includes determining a correctness with regard to an ordering in program code of the release synchronization event and the acquire synchronization event and wherein the properties of the scope order, scope inclusion, and scope transitivity are defined based upon a capability of a system on which program code is being executed.

9. The non-transitory computer-readable storage device of claim 8 , wherein the scope order comprises a strong scope order or a weak scope order.

10. The non-transitory computer-readable storage device of claim 8 , wherein the scope order is a weak scope order, and the release synchronization event and the acquire synchronization event share a same scope.

11. The non-transitory computer-readable storage device of claim 8 , wherein the scope order is a strong scope order, and both scope inclusion and scope transitivity are present in the memory consistency model.

12. The non-transitory computer-readable storage device of claim 8 , wherein the scope order is a strong scope order and scope transitivity is present in the memory consistency model.

13. The non-transitory computer-readable storage device of claim 8 , wherein the scope order is a weak scope order and scope transitivity is present in the memory consistency model.

14. The non-transitory computer-readable storage device of claim 8 , wherein the scope order is a strong scope order and scope inclusion is present in the memory consistency model.

15. A processing unit comprising one or more compute units configured to:
receive a portion of program code, the portion having a first thread and a second thread;
identify a store memory event associated with the first thread and a load memory event associated with the second thread, wherein the store memory event and the load memory share a same variable; and
determine, in accordance with a memory consistency model, when a program is heterogeneous-race-free due to a release synchronization event associated with the first thread and an acquire synchronization event associated with the second thread, the memory consistency model having a property of scope order, scope inclusion, scope transitivity or combination thereof, wherein the determination in accordance with the memory consistency model includes the one or more compute units configured to determine a correctness with regard to an ordering in program code of the release synchronization event and the acquire synchronization event and wherein the properties of the scope order, scope inclusion, scope transitivity are defined based upon a capability of a system on which program code is being executed.

16. The processing unit of claim 15 , wherein the scope order comprises a strong scope order or a weak scope order.

17. The processing unit of claim 16 , wherein the scope order is a strong scope order, and both scope inclusion and scope transitivity are present in the memory consistency model.

18. The processing unit of claim 16 , wherein the scope order is a strong scope order and scope transitivity is present in the memory consistency model.

19. The processing unit of claim 16 , wherein the scope order is a weak scope order and scope transitivity is present in the memory consistency model.

20. The processing unit of claim 15 , wherein the scope order is a weak scope order, and the release synchronization event and the acquire synchronization event share a same scope.

Assignees

• Advanced Micro Devices Inc

Inventors

• Hower Derek R
• Hill Mark D
• Wood David
• Reinhardt Steven K
• Gaster Benedict R
• Hechtman Blake A
• Beckmann Bradford M

Classifications

• G06F9/44 Primary

  Arrangements for executing specific programs · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/524

  Deadlock detection or avoidance · CPC title

• G06F8/454

  Consistency (cache consistency protocols in hierarchically structured memory systems G06F12/0815) · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title