Integrated photonic-mirror test circuit

US9841347B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9841347-B2
Application numberUS-201514947061-A
CountryUS
Kind codeB2
Filing dateNov 20, 2015
Priority dateNov 20, 2015
Publication dateDec 12, 2017
Grant dateDec 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A reflectivity test circuit is described. The reflectivity test circuit includes a symmetric structure that cancels errors in the reflectivity measurements. In particular, the reflectivity test circuit includes an optical waveguide that is optically coupled to two optical ports and two optical couplers. The optical couplers are optically coupled to adjacent optical waveguides, at least one of which is optically coupled to a third optical port and the mirror. Moreover, a length of the optical waveguide is chosen to match the round-trip optical path length in at least the one of the adjacent optical waveguides. During operation, control logic determines the reflectivity of the mirror based at least on a ratio of an optical power measured on one of the two optical ports to an input optical power on the third optical port.

First claim

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What is claimed is: 1. An integrated circuit, comprising a reflectivity test circuit, wherein the reflectivity test circuit includes: a first mirror; a first optical port that, during operation, selectively receives first input optical power; a first optical waveguide having a first end optically coupled to the first mirror and a second end optically coupled to the first optical port; a first optical coupler; a first photodetector that, during operation, measures a first optical power; a second photodetector that, during operation, measures a second optical power; a second optical waveguide optically coupled to the first optical waveguide by the first optical coupler, wherein a first end of the second optical waveguide is optically coupled to the first photodetector and a second end of the second optical waveguide is optically coupled to the second photodetector; and control logic electrically coupled to the first photodetector and the second photodetector, wherein, during operation, the control logic determines a reflectivity of the first mirror based on a first ratio of the first optical power and the second optical power when the first input optical power is received on the first optical port. 2. The integrated circuit of claim 1 , wherein the first optical port includes a vertical grating coupler. 3. The integrated circuit of claim 1 , wherein the integrated circuit comprises: a substrate; a buried-oxide layer disposed on the substrate; and a semiconductor layer disposed on the buried-oxide layer; wherein the first optical waveguide, the first optical coupler and the second optical waveguide are, at least in part, included in the semiconductor layer. 4. The integrated circuit of claim 1 , wherein the first optical waveguide has a first length equal to L and the second optical waveguide has a second length equal to 2·L. 5. The integrated circuit of claim 1 , wherein, during operation, the control logic determines the reflectivity at different wavelengths. 6. The integrated circuit of claim 1 , wherein the first mirror includes a distributed Bragg reflector. 7. The integrated circuit of claim 1 , wherein the reflectivity test circuit includes: a second optical coupler; a first optical waveguide termination; a second optical waveguide termination; and a third optical waveguide optically coupled to the second optical waveguide by the second optical coupler, wherein a first end of the third optical waveguide is optically coupled to the first optical waveguide termination and a second end of the third optical waveguide is optically coupled to the second optical waveguide termination. 8. The integrated circuit of claim 1 , wherein the reflectivity test circuit includes: a second optical coupler; a second mirror; a second optical port that, during operation, selectively receives second input optical power; a third optical waveguide optically coupled to the second optical waveguide by the second optical coupler, wherein a first end of the third optical waveguide is optically coupled to the second mirror and a second end of the third optical waveguide is optically coupled to the second optical port; and wherein during operation, the control logic determines the reflectivity of the first mirror based on a product of the first ratio and a second ratio of the second optical power and the first optical power when the second input optical power is received on the second optical port. 9. The integrated circuit of claim 8 , wherein the second optical port includes a vertical grating coupler. 10. The integrated circuit of claim 8 , wherein the first optical waveguide has a first length equal to L, the second optical waveguide has a second length equal to 2·L, and the third optical waveguide has a third length equal to L. 11. The integrated circuit of claim 8 , wherein, during operation, the control logic determines the reflectivity at different wavelengths. 12. The integrated circuit of claim 8 , wherein the first mirror and the second mirror include distributed Bragg reflectors.

Assignees

Inventors

Classifications

  • Bends, branchings or intersections · CPC title

  • Mirror; Reflectors or the like · CPC title

  • for multiplexing or demultiplexing, i.e. combining or separating wavelengths, e.g. 1xN, NxM · CPC title

  • Coupling light guides with opto-electronic elements · CPC title

  • Optical coupling means (G02B6/36, G02B6/42 take precedence) · CPC title

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Frequently asked questions

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What does patent US9841347B2 cover?
A reflectivity test circuit is described. The reflectivity test circuit includes a symmetric structure that cancels errors in the reflectivity measurements. In particular, the reflectivity test circuit includes an optical waveguide that is optically coupled to two optical ports and two optical couplers. The optical couplers are optically coupled to adjacent optical waveguides, at least one of w…
Who is the assignee on this patent?
Oracle Int Corp
What technology area does this patent fall under?
Primary CPC classification G01M11/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).