Low power buffer with dynamic gain control

Patent metadata

Field	Value
Publication number	US-9837998-B2
Application number	US-201615375048-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Feb 4, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

First claim

What is claimed is:

1. A communication system comprising:
a buffer circuit in a receiver channel of the communication system, the buffer circuit having at least one node to receive at least one gain control signal; and
a gain control signal generation circuit comprising,
a gain control signal node connected to the at least one gain control signal; and
a replica buffer coupled to the gain control signal node, the replica buffer to serve as a proxy for the buffer circuit.

2. The communication system of claim 1 , wherein the gain control signal generation circuit controls a current shunt circuit to shunt a first bypass current to adjust a gain of the buffer circuit.

3. The communication system of claim 1 , wherein the buffer circuit further comprises, a current shunt circuit connected the gain control signal to bias the current shunt circuit to set a gain to a target gain.

4. The communication system claim 3 , wherein the current shunt circuit comprises an N-type MOSFET device.

5. The communication system of claim 3 , further comprising a difference amplifier to generate the gain control signal, wherein the difference amplifier has at least one input coupled to an output of the replica buffer.

6. The communication system of claim 5 , wherein the gain control signal generated by the difference amplifier controls the target gain.

7. The buffer circuit of claim 1 , wherein the gain control signal generation circuit further comprises at least one gain DAC coupled to the gain control signal node, wherein the at least one gain DAC converts a first digital gain control signal to an analog gain control signal.

8. A method for controlling gain in a communication system, the method comprising:
disposing a buffer circuit in a receiver channel of the communication system, the buffer circuit having at least one node to receive at least one gain control signal; and
providing a gain control signal generation circuit comprising,
a gain control signal node connected to the at least one gain control signal; and
a replica buffer coupled to the gain control signal node, the replica buffer to serve as a proxy for the buffer circuit.

9. The method of claim 8 , further comprising, controlling a bias signal of a current shunt circuit to shunt a first bypass current to adjust a gain of the buffer circuit.

10. The method of claim 8 , wherein the buffer circuit further comprises, a current shunt circuit connected the gain control signal to bias the current shunt circuit to set a gain to a target gain.

11. The method of claim 10 , further comprising adjusting the gain control signal by a difference amplifier that has at least one input coupled to an output of the replica buffer.

12. The method of claim 11 , wherein the gain control signal generated by the difference amplifier controls the target gain.

13. The method of claim 8 , wherein the gain control signal generation circuit further comprises at least one gain DAC coupled to the gain control.

Assignees

• Inphi Corp

Inventors

• Gorecki James Lawrence
• Tan han-yuan

Classifications

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F3/3033

  NMOS SEPP output stages (H03F3/3008 takes precedence) · CPC title

• H03F3/45076

  characterised by the way of implementation of the active amplifying circuit in the differential amplifier · CPC title

• H04B1/16

  Circuits · CPC title