Semiconductor device

Patent metadata

Field	Value
Publication number	US-9837519-B2
Application number	US-201615345880-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Feb 5, 2014
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first nitride semiconductor layer that is made over a substrate;
a second nitride semiconductor layer that is formed on the first nitride semiconductor layer;
a third nitride semiconductor layer that is formed on the second nitride semiconductor layer;
a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer;
a gate electrode that is formed over the fourth nitride semiconductor layer;
a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on respective sides of the gate electrode;
a first connection portion that connects the first electrode to the first nitride semiconductor layer;
a second connection portion that connects the second electrode to the second nitride semiconductor layer; and
an insulating film that is formed between the first connection portion and the second nitride semiconductor layer,
wherein the first nitride semiconductor layer contains impurities of a first conductivity type,
wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type,
wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region is a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer,
wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer, and
wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion,
wherein the first electrode extends along a first direction and the first electrode is connected to a first pad extending along a second direction that is perpendicular to the first direction in a plan view.

2. The semiconductor device according to claim 1 ,
wherein the first connection portion is arranged in the second region and formed below the first pad.

3. The semiconductor device according to claim 1 , further comprising:
a trench that penetrates through the fourth nitride semiconductor layer and reaches a middle portion of the third nitride semiconductor layer,
wherein the gate electrode is arranged within the trench through a gate insulating film.

4. The semiconductor device according to claim 1 ,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer.

5. The semiconductor device according to claim 1 ,
wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer.

6. The semiconductor device according to claim 1 ,
wherein the second electrode extends along the first direction and the second electrode is connected to a second pad extending along the second direction in a plan view.

7. The semiconductor device according to claim 6 ,
wherein the second connection portion is arranged in the second region and formed below the second pad.

8. The semiconductor device according to claim 6 ,
wherein the second connection portion is arranged in the first region and formed below the second electrode.

9. The semiconductor device according to claim 1 ,
wherein a superlattice layer is arranged between the substrate and first nitride semiconductor layer, and
wherein in the superlattice layer, two or more stacked bodies having a fifth nitride semiconductor layer, and a sixth nitride semiconductor layer different in electron affinity from the fifth nitride semiconductor layer are repetitively arranged.

10. The semiconductor device according to claim 1 ,
wherein the second connection portion is arranged within a second through-hole that penetrates through the fourth nitride semiconductor layer and the third nitride semiconductor layer, and reaches the second nitride semiconductor layer.

11. A semiconductor device, comprising:
a first nitride semiconductor layer that is made over a substrate;
a second nitride semiconductor layer that is formed on the first nitride semiconductor layer;
a third nitride semiconductor layer that is formed on the second nitride semiconductor layer;
a fourth nitride semiconductor layer that is formed on the third nitride semiconductor layer;
a gate junction nitride semiconductor layer that is formed on the fourth nitride semiconductor layer;
a gate electrode that is arranged above the fourth nitride semiconductor layer through the gate junction nitride semiconductor layer;
a first electrode and a second electrode that are formed above the fourth nitride semiconductor layer on respective sides of the gate electrode;
a first connection portion that connects the first electrode to the first nitride semiconductor layer;
a second connection portion that connects the second electrode to the second nitride semiconductor layer; and
an insulating film that is formed between the first connection portion and the second nitride semiconductor layer,
wherein the first nitride semiconductor layer contains impurities of a first conductivity type,
wherein the second nitride semiconductor layer contains impurities of a second conductivity type that is a conductivity type opposite to the first conductivity type,
wherein the substrate has a first region and a second region,
wherein the gate electrode, the first electrode, and the second electrode are formed in the first region,
wherein the second region is a device isolation region formed in the fourth nitride semiconductor layer and the third nitride semiconductor layer,
wherein the first connection portion is arranged within a first through-hole that penetrates through the device isolation region and the second nitride semiconductor layer, and reaches the first nitride semiconductor layer, and
wherein the insulating film is arranged between a side wall of the first through-hole and the first connection portion
wherein the first electrode extends along a first direction and the first electrode is connected to a first pad extending along a second direction that is perpendicular to the first direction in a plan view.

12. The semiconductor device according to claim 11 ,
wherein the first connection portion is arranged in the second region and formed below the first pad.

13. The semiconductor device according to claim 11 ,
wherein an electron affinity of the fourth nitride semiconductor layer is smaller than an electron affinity of the third nitride semiconductor layer,
wherein an electron affinity of the gate junction nitride semiconductor layer is larger than an electron affinity of the fourth nitride semiconductor layer.

14. The semiconductor device according to claim 11 ,
wherein the second connection portion is arranged within a second through-hole that penetrates through the device isolation region, and reaches the second nitride semiconductor layer.

15. The semiconductor device according to claim 11 ,
wherein the second electrode extends along the first direction and the second electrode is connected to a second pad extending along the second direction in a plan view.

16. The semiconductor device according to claim 15 ,
wherein the second connection portion is arranged in the second region and formed be

Assignees

• Renesas Electronics Corp

Inventors

• Nakayama Tatsuo
• Miyamoto Hironobu
• Okamoto Yasuhiro
• Miura Yoshinao
• Inoue Takashi

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/41766

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/861

  Electricity · mapped topic

• H01L29/155

  Electricity · mapped topic