Method and system for transient voltage suppression

Patent metadata

Field	Value
Publication number	US-8987858-B2
Application number	US-201313846380-A
Country	US
Kind code	B2
Filing date	Mar 18, 2013
Priority date	Mar 18, 2013
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

First claim

The invention claimed is:

1. A transient voltage suppression (TVS) device comprising:
a first layer of wide band gap semiconductor material formed of a first conductivity type material;
a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (μm) and 22.0 μm thick, the second layer operating using punch-through physics; and
a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer,
wherein a junction between said second layer and said third layer comprises an edge region that comprises a sidewall extending substantially perpendicular to the second and third layers through the third layer and partially into the second layer, wherein the edge region has a relatively higher resistance than the remainder of the second layer and the third layer.

2. The device of claim 1 , wherein said first layer, said second layer and said third layer comprises an epitaxial structure where the molecular arrangement of one of said first layer, said second layer and said third layer is defined by the crystallographic and chemical features of an adjacent one of said first layer, said second layer and said third layer.

3. The device of claim 1 , wherein said second layer comprises a relatively lightly doped n− epitaxy layer converted to a p− conductivity layer having an ion implanted structure.

4. The device of claim 1 , wherein said third layer comprises a relatively lightly doped n− epitaxy layer converted an n+ layer having an ion implanted structure.

5. A transient voltage suppression semiconductor device, comprising:
a substrate of a wide band gap semiconductor material;
a first layer of a first conductivity type on the substrate;
a second layer of a second conductivity type on the first layer, the second layer operating using punch-through physics; and
a third layer of the first conductivity type on the second layer, wherein
an edge region of the first, second and third layers has a mesa structure having a beveled sidewall angled about five to about eighty degrees with respect to an interface between adjacent layers, the third layer and a portion of the second layer having a sidewall that is substantially perpendicular to the substrate.

6. The device of claim 5 , wherein the wind band gap semiconductor material is silicon carbide.

7. The device of claim 5 , wherein the second and third layers are epitaxially grown layers.

8. The device of claim 7 , wherein the second and third layers are formed by ion implantation of the epitaxially grown layers.

9. The device of claim 5 , wherein the substrate is doped with dopants of the first conductivity and the first layer is a doped epitaxy layer formed on the substrate.

10. The device of claim 5 , wherein the second layer is relatively lightly doped relative to the first and third layers.

11. The device of claim 5 , wherein the substrate and the first, second, and third layers have a uniform doping concentration.

12. The device of claim 5 , wherein a first peak electric field of a first junction between the first and second layers and a second peak electric field of a second junction between the second and third layers are substantially symmetrical.

13. The device of claim 5 , wherein the device is sized and formed to have a maximum internal electric field internal less than about two megavolts per centimeter.

14. The device of claim 5 , wherein an electrical leakage current of the device is less than approximately 1.0 microamp up to approximately the punch-through voltage of the semiconductor device at room temperature and less than 100.0 microamp up to approximately the punch-through voltage at operating temperatures of up to 225° C.

15. The device of claim 5 , wherein the second layer exhibits punch-through characteristics between approximately 5.0 volts to approximately 200.0 volts.

Assignees

• Gen Electric

Inventors

• Kashyap Avinash Srikrishnan
• Sandvik Peter Micah
• Arthur Stephen Daley

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D62/8325 Primary

  Silicon carbide · CPC title