Forming strained and unstrained features on a substrate

Patent metadata

Field	Value
Publication number	US-9837408-B1
Application number	US-201615278420-A
Country	US
Kind code	B1
Filing date	Sep 28, 2016
Priority date	Sep 28, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Embodiments are directed to a method of forming features of a semiconductor device. The method includes forming a first feature including a first type of semiconductor material, which can be tensile or can have compressive strain. The method further includes forming an enclosure structure including a second type of semiconductor material, wherein the first feature includes first feature sidewall surfaces extending around a circumference of the first feature. The enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.

First claim

What is claimed is:

1. A method of forming features of a semiconductor device, the method comprising:
forming a first feature comprising a first type of semiconductor material; and
forming an enclosure structure comprising a second type of semiconductor material;
wherein the first feature comprises first feature sidewall surfaces extending around a circumference of the first feature;
wherein the enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.

2. The method of claim 1 , wherein forming the enclosure structure comprises:
forming a second feature comprising the second type of semiconductor material; and
forming a trench in the second feature;
wherein forming the trench defines sidewalls structures in the second feature that surround the trench.

3. The method of claim 2 , wherein forming the first feature comprises depositing the first type of material in the trench.

4. The method of claim 3 , wherein depositing the first type of material in the trench comprises epitaxially growing the first type of material in the trench.

5. The method of claim 3 , wherein the second feature comprises a fin.

6. The method of claim 3 , wherein the second feature is formed from a substrate comprising the second type of semiconductor material.

7. The method of claim 6 , wherein:
the first type of semiconductor material comprises silicon germanium; and
the second type of semiconductor material comprises silicon.

8. A method of forming features of a semiconductor device, the method comprising:
forming a first feature on a substrate, wherein the first feature and the substrate comprise a first type of semiconductor material;
forming a trench in the first feature, wherein the trench defines sidewall structures in the first feature that surround the trench; and
forming a second feature comprising a second type of semiconductor material;
wherein forming the second feature comprises filling the trench with the second type of material such that the sidewall structures in the first feature extend around a circumference of the second feature.

9. The method of claim 8 , wherein filling the trench comprises depositing the second type of material in the trench.

10. The method of claim 9 , wherein depositing the second type of material comprises epitaxially growing the second type of material in the trench.

11. The method of claim 8 , wherein:
the first feature comprises a first fin; and
the second feature comprises a second fin.

12. The method of claim 8 , wherein:
the first type of semiconductor material comprises silicon; and
the second type of semiconductor material comprises silicon germanium.

13. The method of claim 8 further comprising forming a gate structure that:
extends over a portion of the sidewall structures in the first feature; and
extends over a portion of the second feature.

14. The method of claim 13 wherein forming the gate structure comprises applying etch processes that at least partially etch the sidewall structures in the first feature but do not etch portions of the second feature that are covered by the sidewall structures in the first feature.

15. The method of claim 8 further comprising forming a third feature on the substrate, wherein the third feature and the substrate comprise the first type of semiconductor material.

16. The method of claim 15 further comprising:
forming a first gate structure over a portion of the sidewall structures and over a portion of the second feature; and
forming a second gate structure over a portion of the third feature.

17. A semiconductor device comprising:
a substrate comprising a first type of semiconductor material;
a first feature on the substrate, wherein the first feature comprises the first type of semiconductor material;
a trench in the first feature, wherein the trench defines sidewall structures in the first feature that surround the trench; and
a second feature within the trench, wherein the second feature comprises a second type of semiconductor, wherein the sidewall structures in the first feature extend around a circumference of the second feature.

18. The semiconductor device of claim 17 , wherein:
the first feature comprises a first fin;
the second feature comprises a second fin;
the first type of semiconductor material comprises silicon; and
the second type of semiconductor material comprises silicon germanium.

19. The semiconductor device of claim 17 further comprising a third feature on the substrate, wherein the third feature comprises the first type of semiconductor material.

20. The semiconductor device of claim 19 further comprising:
a first gate structure over a portion of the sidewall structures and a portion of the second feature; and
a second gate structure over a portion third feature.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Xu Peng
• Xu Zheng

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H01L27/0886 Primary

  Electricity · mapped topic