Systems and methods for creating fluidic assembly structures on a substrate

Patent metadata

Field	Value
Publication number	US-9837390-B1
Application number	US-201615344736-A
Country	US
Kind code	B1
Filing date	Nov 7, 2016
Priority date	Nov 7, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Embodiments are related to fluidic assembly and, more particularly, to systems and methods for forming physical structures on a substrate.

First claim

What is claimed is:

1. An assembly panel, the panel comprising:
a substrate having a top surface;
an electronics structure layer disposed over the top layer of the substrate;
a sol-gel based structural layer disposed over the top layer of the substrate and the electronics structure layer, wherein the sol-gel based structural layer includes openings exposing at least a part of the electronics structure layer; and
wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of: hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.

2. The assembly panel of claim 1 , wherein the electronics structure layer exhibits a first thickness and the sol-gel based structural layer exhibits a second thickness, and wherein the second thickness is at least three times thicker than the first thickness.

3. The assembly panel of claim 2 , wherein the second thickness is at least five times thicker than the first thickness.

4. The assembly panel of claim 1 , wherein the electronics structure layer includes an electrically conductive material connecting a bottom area of a first of the openings to a bottom area of a second of the openings.

5. The assembly panel of claim 1 , wherein a material of the substrate is selected from a group consisting of: polymer, metal, ceramic, glass, and glass-ceramic.

6. The assembly panel of claim 1 , wherein vias extend through the substrate from the bottom of a subset of the openings.

7. The assembly panel of claim 1 , wherein the substrate is a multi-layer substrate.

8. A method for manufacturing a device, the method comprising:
providing a substrate; and
forming a sol-gel based structural layer over the substrate using a solution-based process, wherein the sol-gel structural layer includes features having varying feature depths.

9. The method of claim 8 , wherein the solution-based process is a subtractive process.

10. The method of claim 8 , wherein the varying feature depth includes openings in the sol-gel based structural layer through which an underlying layer is exposed.

11. The method of claim 10 , wherein the method further comprises:
forming an electronics structure layer over the substrate prior to forming the sol-gel based structural layer over the substrate such that the sol-gel based structural layer covers at least a portion of the electronics structure layer; and
wherein the underlying layer is selected from a group consisting of: the electronics structure layer, and the top surface of the substrate.

12. The method of claim 11 , the method further comprising:
using fluidic assembly to deposit micro-devices in the openings; and
forming an encapsulation layer over the sol-gel based structural layer and the micro-devices.

13. The method of claim 12 , wherein the micro-devices are light emitting diodes.

14. The method of claim 12 , wherein forming the encapsulation layer includes depositing a sol-gel material over the substrate, and curing the sol-gel material.

15. The method of claim 8 , wherein the solution-based process is an additive process, and wherein the additive process is selected from a group of: a replication process, a stamping process, and a printing process.

16. The method of claim 8 , wherein the solution-based process is an additive process, and wherein the additive process is a printing process, and wherein the printing process is selected from a group consisting of: screen printing, flexo printing, gravure printing, inkjet printing, and offset printing.

17. The method of claim 8 , wherein the solution-based process is an additive process, and wherein the additive process includes curing a sol-gel material added over the substrate.

18. The method of claim 17 , wherein curing the sol-gel material added over the substrate includes a process selected from a group consisting of: exposing the sol-gel material to ultraviolet radiation, and exposing the sol-gel material to thermal radiation.

19. The method of claim 8 , wherein the method further comprises:
forming an electronics structure layer over the substrate prior to forming the sol-gel based structural layer over the substrate such that the sol-gel based structural layer covers at least a portion of the electronics structure layer.

20. The method of claim 8 , wherein vias extend through the substrate from the bottom of a subset of the openings.

21. An electronic display device, the display device comprising:
a substrate;
an electronics structure layer formed over the substrate and including a first electrically conductive trace;
a sol-gel based structural layer formed over the substrate such that the sol-gel based structural layer covers a first portion of the electronics structure layer, wherein the sol-gel structural layer includes openings though which a second portion of the electronics structure layer is exposed, and wherein the first electrically conductive trace electrically connects the bottom of at least two of the openings;
light emitting diodes each within a respective one of the openings, wherein the light emitting diodes each include an upper electrical contact and a lower electrical contact, and wherein the lower electrical contact of a subset of the light emitting diodes is electrically connected to the first electrically conductive trace;
an encapsulation layer covering at least a portion of the sol-gel based structural layer and micro-devices; and
a second electrically conductive trace electrically connecting the upper electrical contacts of two or more of the light emitting diodes.

22. The electronic display device of claim 21 , wherein the electronics structure layer exhibits a first thickness and the sol-gel based structural layer exhibits a second thickness, and wherein the second thickness is at least three times thicker than the first thickness.

23. The electronic display device of claim 22 , wherein the second thickness is at least five times thicker than the first thickness.

24. The electronic display device of claim 21 , wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of: a silane, a silicate, and water.

25. The electronic display device of claim 21 , wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of: hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.

26. The electronic display device of claim 21 , wherein a material of the substrate is selected from a group consisting of: polymer, metal, ceramic, glass, and glass-ceramic.

27. The electronic display device of claim 21 , wherein vias extend through the substrate from the bottom of a subset of the openings.

28. The electronic display device of claim 21 , wherein the substrate is a multi-layer substrate.

29. An assembly panel, the panel comprising:
a substrate having a top surface;
a sol-gel based structural layer disposed adjacent to the top surface of the substrate;
an electronics structure layer disposed over the sol-gel based structural layer such that the electronics structure layer is separated from the substrate by the sol-gel structural layer; and

Assignees

• Corning Inc

Inventors

• Sorensen Michael Lesley
• Garner Sean Mathew

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title