Nonvolatile semiconductor storage device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-8981522-B2
Application number	US-201314010662-A
Country	US
Kind code	B2
Filing date	Aug 27, 2013
Priority date	Jan 17, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A nonvolatile semiconductor storage device includes a substrate; an isolation film extending in a first direction and dividing the substrate into element regions; a cell string including memory cells in the element regions; a cell unit including the cell string and a select transistor on first directional ends of the cell string; diffusion layers formed in a portion of the element region first directionally beside the select gate electrode, the diffusion layers being adjacent to one another in a second direction intersecting with the first direction; and contacts extending through an interlayer insulating film and contacting the diffusion layers. An upper surface of the isolation film located between the diffusion layers is lower than an upper surface of the substrate. A laminate of silicon oxide film and a silicon nitride film are located above the upper surface of the isolation film and below the upper surface of the substrate.

First claim

What is claimed is:

1. A nonvolatile semiconductor storage device, comprising:
a semiconductor substrate;
an element isolation film that extends in a first direction and that divides the semiconductor substrate into a plurality of element regions;
a cell string including a plurality of memory cells disposed along the first direction in the element regions;
a cell unit including the cell string and a select transistor located on each of ends of the cell string in the first direction;
a plurality of diffusion layers each formed in a portion of the element region located beside the select gate electrode in the first direction, each of the diffusion layers being arranged to be adjacent to one another in a second direction intersecting with the first direction;
an interlayer insulating film formed above the plurality of diffusion layers; and
a plurality of contacts extending through the interlayer insulating film and contacting the diffusion layers respectively;
wherein an upper surface the element isolation film located between the diffusion layers is lower than an upper surface of the semiconductor substrate; and
wherein a silicon oxide film and a silicon nitride film disposed above the silicon oxide film are provided above the upper surface of the element isolation film and below the upper surface of the semiconductor substrate.

2. The device according to claim 1 , wherein a bottom surface of each of the diffusion layers is lower than the upper surface of the element isolation film.

3. The device according to claim 1 , wherein the silicon oxide film forms a recess between the adjacent diffusion layers, and wherein the silicon nitride film includes a first silicon nitride film formed along an inner side of the recess and a second silicon nitride film formed above the first silicon nitride film.

4. The device according to claim 3 , wherein the second silicon nitride film is thicker than the first silicon nitride film.

5. The device according to claim 3 , wherein the first silicon nitride film contains carbon.

6. The device according to claim 3 , wherein the second silicon nitride film contains carbon.

7. The device according to claim 1 , wherein the semiconductor substrate is a silicon substrate, and wherein each of the diffusion layers contains arsenic.

8. The device according to claim 1 , wherein the contact includes a bottom surface which is higher than the lowermost surface of the first silicon nitride film.

Assignees

• Toshiba Kk

Inventors

• Fujii Kenichi
• Yotsumoto Akira
• Yamanaka Takaya
• Kikushima Fumie

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H01L21/76224 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic